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<div class="title">xtrafgen_hw.h File Reference</div>  </div>
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Macros</h2></td></tr>
<tr class="memitem:affb7c95abd8cad50d7efa83f94ea3344"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344">XTrafGen_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;(Xil_In32(((BaseAddress) + (RegOffset))))</td></tr>
<tr class="memdesc:affb7c95abd8cad50d7efa83f94ea3344"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_ReadReg returns the value read from the register specified by <em>RegOffset</em>.  <a href="#affb7c95abd8cad50d7efa83f94ea3344">More...</a><br /></td></tr>
<tr class="separator:affb7c95abd8cad50d7efa83f94ea3344"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac6e57b26c1f5674deb7c571dc319bf9e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e">XTrafGen_WriteReg</a>(BaseAddress,  RegOffset,  Data)&#160;&#160;&#160;Xil_Out32(((BaseAddress) + (RegOffset)), (Data))</td></tr>
<tr class="memdesc:ac6e57b26c1f5674deb7c571dc319bf9e"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_WriteReg, writes <em>Data</em> to the register specified by <em>RegOffset</em>.  <a href="#ac6e57b26c1f5674deb7c571dc319bf9e">More...</a><br /></td></tr>
<tr class="separator:ac6e57b26c1f5674deb7c571dc319bf9e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a29995f5e78072a8756081fed9ccb36bd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a29995f5e78072a8756081fed9ccb36bd">XTrafGen_ReadParamRam</a>(BaseAddress,  Offset)&#160;&#160;&#160;(Xil_In32(((BaseAddress) + <a class="el" href="group__trafgen__v3__2.html#ga3252ba966b4231b39738858474879b33">XTG_PARAM_RAM_OFFSET</a> + (Offset))))</td></tr>
<tr class="memdesc:a29995f5e78072a8756081fed9ccb36bd"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_ReadParamRam returns the value read from the Parameter RAM specified by <em>Offset</em>.  <a href="#a29995f5e78072a8756081fed9ccb36bd">More...</a><br /></td></tr>
<tr class="separator:a29995f5e78072a8756081fed9ccb36bd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:affbc767805f25351f801dc04114d513f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#affbc767805f25351f801dc04114d513f">XTrafGen_WriteParamRam</a>(BaseAddress,  Offset,  Data)&#160;&#160;&#160;Xil_Out32(((BaseAddress) + <a class="el" href="group__trafgen__v3__2.html#ga3252ba966b4231b39738858474879b33">XTG_PARAM_RAM_OFFSET</a> + (Offset)), (Data))</td></tr>
<tr class="memdesc:affbc767805f25351f801dc04114d513f"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_WriteParamRam, writes <em>Data</em> to the Parameter RAM specified by <em>Offset</em>.  <a href="#affbc767805f25351f801dc04114d513f">More...</a><br /></td></tr>
<tr class="separator:affbc767805f25351f801dc04114d513f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a04a570c3b4cc407d745237050374013c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a04a570c3b4cc407d745237050374013c">XTrafGen_ReadCmdRam</a>(BaseAddress,  Offset)&#160;&#160;&#160;(Xil_In32(((BaseAddress) + <a class="el" href="group__trafgen__v3__2.html#ga1b4f5daeb95b5827db0760c1c0dc13e5">XTG_COMMAND_RAM_OFFSET</a> + (Offset))))</td></tr>
<tr class="memdesc:a04a570c3b4cc407d745237050374013c"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_ReadCmdRam returns the value read from the Command RAM specified by <em>Offset</em>.  <a href="#a04a570c3b4cc407d745237050374013c">More...</a><br /></td></tr>
<tr class="separator:a04a570c3b4cc407d745237050374013c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab9c29e9e8361e7dc553c689e7cfd8ee1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#ab9c29e9e8361e7dc553c689e7cfd8ee1">XTrafGen_ReadCmdRam_Msb</a>(BaseAddress,  Offset)&#160;&#160;&#160;(Xil_In32(((BaseAddress) + <a class="el" href="group__trafgen__v3__2.html#ga6fd650735d7eb15cc3cd76679f8b7894">XTG_COMMAND_RAM_MSB_OFFSET</a> + (Offset))))</td></tr>
<tr class="memdesc:ab9c29e9e8361e7dc553c689e7cfd8ee1"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_ReadCmdRam_Msb returns the value read from the Command RAM specified by <em>Offset</em>.  <a href="#ab9c29e9e8361e7dc553c689e7cfd8ee1">More...</a><br /></td></tr>
<tr class="separator:ab9c29e9e8361e7dc553c689e7cfd8ee1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a25bf6ea33be9bb74e718dc810c6760f5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a25bf6ea33be9bb74e718dc810c6760f5">XTrafGen_WriteCmdRam</a>(BaseAddress,  Offset,  Data)&#160;&#160;&#160;Xil_Out32(((BaseAddress) + <a class="el" href="group__trafgen__v3__2.html#ga1b4f5daeb95b5827db0760c1c0dc13e5">XTG_COMMAND_RAM_OFFSET</a> + (Offset)), (Data))</td></tr>
<tr class="memdesc:a25bf6ea33be9bb74e718dc810c6760f5"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_WriteCmdRam, writes <em>Data</em> to the Command RAM specified by <em>Offset</em>.  <a href="#a25bf6ea33be9bb74e718dc810c6760f5">More...</a><br /></td></tr>
<tr class="separator:a25bf6ea33be9bb74e718dc810c6760f5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afebb93dc8864de6d9466a5fd6355c117"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#afebb93dc8864de6d9466a5fd6355c117">XTrafGen_WriteCmdRam_Msb</a>(BaseAddress,  Offset,  Data)&#160;&#160;&#160;Xil_Out32(((BaseAddress) + <a class="el" href="group__trafgen__v3__2.html#ga6fd650735d7eb15cc3cd76679f8b7894">XTG_COMMAND_RAM_MSB_OFFSET</a> + (Offset)), (Data))</td></tr>
<tr class="memdesc:afebb93dc8864de6d9466a5fd6355c117"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_WriteCmdRam_Msb, writes <em>Data</em> to the Command RAM specified by <em>Offset</em>.  <a href="#afebb93dc8864de6d9466a5fd6355c117">More...</a><br /></td></tr>
<tr class="separator:afebb93dc8864de6d9466a5fd6355c117"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a60ceec5d839e8a8f1cdda74c93c425b8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a60ceec5d839e8a8f1cdda74c93c425b8">XTrafGen_ReadMasterRam</a>(BaseAddress,  Offset)&#160;&#160;&#160;(Xil_In32(((BaseAddress) + <a class="el" href="group__trafgen__v3__2.html#ga5f8872e23f0ea33fda1193c114fa9224">XTG_MASTER_RAM_OFFSET</a> + (Offset))))</td></tr>
<tr class="memdesc:a60ceec5d839e8a8f1cdda74c93c425b8"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_ReadMasterRam returns the value read from the Master RAM specified by <em>Offset</em>.  <a href="#a60ceec5d839e8a8f1cdda74c93c425b8">More...</a><br /></td></tr>
<tr class="separator:a60ceec5d839e8a8f1cdda74c93c425b8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8fe8b5ce12fefb6bba6acee1b89cb2a7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a8fe8b5ce12fefb6bba6acee1b89cb2a7">XTrafGen_WriteMasterRam</a>(BaseAddress,  Offset,  Data)&#160;&#160;&#160;Xil_Out32(((BaseAddress) + <a class="el" href="group__trafgen__v3__2.html#ga5f8872e23f0ea33fda1193c114fa9224">XTG_MASTER_RAM_OFFSET</a> + (Offset)), (Data))</td></tr>
<tr class="memdesc:a8fe8b5ce12fefb6bba6acee1b89cb2a7"><td class="mdescLeft">&#160;</td><td class="mdescRight">XTrafGen_WriteMasterRam, writes <em>Data</em> to the Master RAM specified by <em>Offset</em>.  <a href="#a8fe8b5ce12fefb6bba6acee1b89cb2a7">More...</a><br /></td></tr>
<tr class="separator:a8fe8b5ce12fefb6bba6acee1b89cb2a7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Device registers</div></td></tr>
<tr class="memitem:ga2aee9e721b35ce512abb502ede5b8a06"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga2aee9e721b35ce512abb502ede5b8a06">XTG_MCNTL_OFFSET</a>&#160;&#160;&#160;0x00</td></tr>
<tr class="memdesc:ga2aee9e721b35ce512abb502ede5b8a06"><td class="mdescLeft">&#160;</td><td class="mdescRight">Master Control.  <a href="group__trafgen__v3__2.html#ga2aee9e721b35ce512abb502ede5b8a06">More...</a><br /></td></tr>
<tr class="separator:ga2aee9e721b35ce512abb502ede5b8a06"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga16ab165b5d7fd7c84206606b1bc2dcfa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga16ab165b5d7fd7c84206606b1bc2dcfa">XTG_SCNTL_OFFSET</a>&#160;&#160;&#160;0x04</td></tr>
<tr class="memdesc:ga16ab165b5d7fd7c84206606b1bc2dcfa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave Control.  <a href="group__trafgen__v3__2.html#ga16ab165b5d7fd7c84206606b1bc2dcfa">More...</a><br /></td></tr>
<tr class="separator:ga16ab165b5d7fd7c84206606b1bc2dcfa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6d44ba5c998cf48c8162812f1b183cfa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga6d44ba5c998cf48c8162812f1b183cfa">XTG_ERR_STS_OFFSET</a>&#160;&#160;&#160;0x08</td></tr>
<tr class="memdesc:ga6d44ba5c998cf48c8162812f1b183cfa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Error Status.  <a href="group__trafgen__v3__2.html#ga6d44ba5c998cf48c8162812f1b183cfa">More...</a><br /></td></tr>
<tr class="separator:ga6d44ba5c998cf48c8162812f1b183cfa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga54f00a5d7ea7acb0a8917b79f6aeeb57"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga54f00a5d7ea7acb0a8917b79f6aeeb57">XTG_ERR_EN_OFFSET</a>&#160;&#160;&#160;0x0C</td></tr>
<tr class="memdesc:ga54f00a5d7ea7acb0a8917b79f6aeeb57"><td class="mdescLeft">&#160;</td><td class="mdescRight">Error Enable.  <a href="group__trafgen__v3__2.html#ga54f00a5d7ea7acb0a8917b79f6aeeb57">More...</a><br /></td></tr>
<tr class="separator:ga54f00a5d7ea7acb0a8917b79f6aeeb57"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8549ea88039b3f646e33299b490b8904"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga8549ea88039b3f646e33299b490b8904">XTG_MSTERR_INTR_OFFSET</a>&#160;&#160;&#160;0x10</td></tr>
<tr class="memdesc:ga8549ea88039b3f646e33299b490b8904"><td class="mdescLeft">&#160;</td><td class="mdescRight">Master Err Interrupt Enable.  <a href="group__trafgen__v3__2.html#ga8549ea88039b3f646e33299b490b8904">More...</a><br /></td></tr>
<tr class="separator:ga8549ea88039b3f646e33299b490b8904"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadf7e15dfd4ecd23278ff780bf4369058"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gadf7e15dfd4ecd23278ff780bf4369058">XTG_CFG_STS_OFFSET</a>&#160;&#160;&#160;0x14</td></tr>
<tr class="memdesc:gadf7e15dfd4ecd23278ff780bf4369058"><td class="mdescLeft">&#160;</td><td class="mdescRight">Config Status.  <a href="group__trafgen__v3__2.html#gadf7e15dfd4ecd23278ff780bf4369058">More...</a><br /></td></tr>
<tr class="separator:gadf7e15dfd4ecd23278ff780bf4369058"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadad67dedb6f0b5c0e7aed2e0d62e08eb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gadad67dedb6f0b5c0e7aed2e0d62e08eb">XTG_STREAM_CNTL_OFFSET</a>&#160;&#160;&#160;0x30</td></tr>
<tr class="memdesc:gadad67dedb6f0b5c0e7aed2e0d62e08eb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Streaming Control.  <a href="group__trafgen__v3__2.html#gadad67dedb6f0b5c0e7aed2e0d62e08eb">More...</a><br /></td></tr>
<tr class="separator:gadad67dedb6f0b5c0e7aed2e0d62e08eb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0faa9082cff01c4e5e53bb957b69dae2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga0faa9082cff01c4e5e53bb957b69dae2">XTG_STREAM_CFG_OFFSET</a>&#160;&#160;&#160;0x34</td></tr>
<tr class="memdesc:ga0faa9082cff01c4e5e53bb957b69dae2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Streaming Config.  <a href="group__trafgen__v3__2.html#ga0faa9082cff01c4e5e53bb957b69dae2">More...</a><br /></td></tr>
<tr class="separator:ga0faa9082cff01c4e5e53bb957b69dae2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga476caa717b80c4d276d7ff98aae5f3ca"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga476caa717b80c4d276d7ff98aae5f3ca">XTG_STREAM_TL_OFFSET</a>&#160;&#160;&#160;0x38</td></tr>
<tr class="memdesc:ga476caa717b80c4d276d7ff98aae5f3ca"><td class="mdescLeft">&#160;</td><td class="mdescRight">Streaming Transfer Length.  <a href="group__trafgen__v3__2.html#ga476caa717b80c4d276d7ff98aae5f3ca">More...</a><br /></td></tr>
<tr class="separator:ga476caa717b80c4d276d7ff98aae5f3ca"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafee2ca23e3fc2ed4964740ba69dde023"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gafee2ca23e3fc2ed4964740ba69dde023">XTG_STATIC_CNTL_OFFSET</a>&#160;&#160;&#160;0x60</td></tr>
<tr class="memdesc:gafee2ca23e3fc2ed4964740ba69dde023"><td class="mdescLeft">&#160;</td><td class="mdescRight">Static Mode Register Descrptions.  <a href="group__trafgen__v3__2.html#gafee2ca23e3fc2ed4964740ba69dde023">More...</a><br /></td></tr>
<tr class="separator:gafee2ca23e3fc2ed4964740ba69dde023"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1813133f0d9bd28861fac1a854137411"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga1813133f0d9bd28861fac1a854137411">XTG_STATIC_LEN_OFFSET</a>&#160;&#160;&#160;0x64</td></tr>
<tr class="memdesc:ga1813133f0d9bd28861fac1a854137411"><td class="mdescLeft">&#160;</td><td class="mdescRight">Static Length.  <a href="group__trafgen__v3__2.html#ga1813133f0d9bd28861fac1a854137411">More...</a><br /></td></tr>
<tr class="separator:ga1813133f0d9bd28861fac1a854137411"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Internal RAM Offsets</div></td></tr>
<tr class="memitem:ga3252ba966b4231b39738858474879b33"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga3252ba966b4231b39738858474879b33">XTG_PARAM_RAM_OFFSET</a>&#160;&#160;&#160;0x1000</td></tr>
<tr class="memdesc:ga3252ba966b4231b39738858474879b33"><td class="mdescLeft">&#160;</td><td class="mdescRight">Parameter RAM Offset.  <a href="group__trafgen__v3__2.html#ga3252ba966b4231b39738858474879b33">More...</a><br /></td></tr>
<tr class="separator:ga3252ba966b4231b39738858474879b33"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1b4f5daeb95b5827db0760c1c0dc13e5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga1b4f5daeb95b5827db0760c1c0dc13e5">XTG_COMMAND_RAM_OFFSET</a>&#160;&#160;&#160;0x8000</td></tr>
<tr class="memdesc:ga1b4f5daeb95b5827db0760c1c0dc13e5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Command RAM Offset.  <a href="group__trafgen__v3__2.html#ga1b4f5daeb95b5827db0760c1c0dc13e5">More...</a><br /></td></tr>
<tr class="separator:ga1b4f5daeb95b5827db0760c1c0dc13e5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5f8872e23f0ea33fda1193c114fa9224"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga5f8872e23f0ea33fda1193c114fa9224">XTG_MASTER_RAM_OFFSET</a>&#160;&#160;&#160;0xC000</td></tr>
<tr class="memdesc:ga5f8872e23f0ea33fda1193c114fa9224"><td class="mdescLeft">&#160;</td><td class="mdescRight">Master RAM Offset.  <a href="group__trafgen__v3__2.html#ga5f8872e23f0ea33fda1193c114fa9224">More...</a><br /></td></tr>
<tr class="separator:ga5f8872e23f0ea33fda1193c114fa9224"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6fd650735d7eb15cc3cd76679f8b7894"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga6fd650735d7eb15cc3cd76679f8b7894">XTG_COMMAND_RAM_MSB_OFFSET</a>&#160;&#160;&#160;0xa000</td></tr>
<tr class="memdesc:ga6fd650735d7eb15cc3cd76679f8b7894"><td class="mdescLeft">&#160;</td><td class="mdescRight">Command RAM MSB Offset.  <a href="group__trafgen__v3__2.html#ga6fd650735d7eb15cc3cd76679f8b7894">More...</a><br /></td></tr>
<tr class="separator:ga6fd650735d7eb15cc3cd76679f8b7894"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Master Control Register bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XTG_MCNTL_OFFSET register. </p>
</div></td></tr>
<tr class="memitem:ga2197ba1e4ea908189bc7d77e70ba5a06"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga2197ba1e4ea908189bc7d77e70ba5a06">XTG_MCNTL_REV_MASK</a>&#160;&#160;&#160;0xFF000000</td></tr>
<tr class="memdesc:ga2197ba1e4ea908189bc7d77e70ba5a06"><td class="mdescLeft">&#160;</td><td class="mdescRight">Core Revision Mask.  <a href="group__trafgen__v3__2.html#ga2197ba1e4ea908189bc7d77e70ba5a06">More...</a><br /></td></tr>
<tr class="separator:ga2197ba1e4ea908189bc7d77e70ba5a06"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga912b534ed07c85f5147d86a5125e6cd8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga912b534ed07c85f5147d86a5125e6cd8">XTG_MCNTL_MSTID_MASK</a>&#160;&#160;&#160;0x00E00000</td></tr>
<tr class="memdesc:ga912b534ed07c85f5147d86a5125e6cd8"><td class="mdescLeft">&#160;</td><td class="mdescRight">M_ID_WIDTH Mask.  <a href="group__trafgen__v3__2.html#ga912b534ed07c85f5147d86a5125e6cd8">More...</a><br /></td></tr>
<tr class="separator:ga912b534ed07c85f5147d86a5125e6cd8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf8fafcd0c1061fbf9d6d61680a251309"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gaf8fafcd0c1061fbf9d6d61680a251309">XTG_MCNTL_MSTEN_MASK</a>&#160;&#160;&#160;0x00100000</td></tr>
<tr class="memdesc:gaf8fafcd0c1061fbf9d6d61680a251309"><td class="mdescLeft">&#160;</td><td class="mdescRight">Master Logic Enable Mask.  <a href="group__trafgen__v3__2.html#gaf8fafcd0c1061fbf9d6d61680a251309">More...</a><br /></td></tr>
<tr class="separator:gaf8fafcd0c1061fbf9d6d61680a251309"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga736a0c4efcd60c172f0c5b5bc19fa11b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga736a0c4efcd60c172f0c5b5bc19fa11b">XTG_MCNTL_LOOPEN_MASK</a>&#160;&#160;&#160;0x00080000</td></tr>
<tr class="memdesc:ga736a0c4efcd60c172f0c5b5bc19fa11b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Loop enable Mask.  <a href="group__trafgen__v3__2.html#ga736a0c4efcd60c172f0c5b5bc19fa11b">More...</a><br /></td></tr>
<tr class="separator:ga736a0c4efcd60c172f0c5b5bc19fa11b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga07d0697117d702e5a767bc8cc5083ea0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga07d0697117d702e5a767bc8cc5083ea0">XTG_MCNTL_REV_SHIFT</a>&#160;&#160;&#160;24</td></tr>
<tr class="memdesc:ga07d0697117d702e5a767bc8cc5083ea0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Core Rev shift.  <a href="group__trafgen__v3__2.html#ga07d0697117d702e5a767bc8cc5083ea0">More...</a><br /></td></tr>
<tr class="separator:ga07d0697117d702e5a767bc8cc5083ea0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab849a5c24ef2753d38f62531ed5dcba9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gab849a5c24ef2753d38f62531ed5dcba9">XTG_MCNTL_MSTID_SHIFT</a>&#160;&#160;&#160;21</td></tr>
<tr class="memdesc:gab849a5c24ef2753d38f62531ed5dcba9"><td class="mdescLeft">&#160;</td><td class="mdescRight">M_ID_WIDTH shift.  <a href="group__trafgen__v3__2.html#gab849a5c24ef2753d38f62531ed5dcba9">More...</a><br /></td></tr>
<tr class="separator:gab849a5c24ef2753d38f62531ed5dcba9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Slave Control Register bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XTG_SCNTL_OFFSET register. </p>
</div></td></tr>
<tr class="memitem:ga8a90a170c2c59e105bca09bf32cc5762"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga8a90a170c2c59e105bca09bf32cc5762">XTG_SCNTL_BLKRD_MASK</a>&#160;&#160;&#160;0x00080000</td></tr>
<tr class="memdesc:ga8a90a170c2c59e105bca09bf32cc5762"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable Block Read.  <a href="group__trafgen__v3__2.html#ga8a90a170c2c59e105bca09bf32cc5762">More...</a><br /></td></tr>
<tr class="separator:ga8a90a170c2c59e105bca09bf32cc5762"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga68091fdd6f9b82d0d6bf65c92b131e38"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga68091fdd6f9b82d0d6bf65c92b131e38">XTG_SCNTL_DISEXCL_MASK</a>&#160;&#160;&#160;0x00040000</td></tr>
<tr class="memdesc:ga68091fdd6f9b82d0d6bf65c92b131e38"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable Exclusive Access.  <a href="group__trafgen__v3__2.html#ga68091fdd6f9b82d0d6bf65c92b131e38">More...</a><br /></td></tr>
<tr class="separator:ga68091fdd6f9b82d0d6bf65c92b131e38"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga05a3dd5b5ff4ddb1ed8bd33f091893d3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga05a3dd5b5ff4ddb1ed8bd33f091893d3">XTG_SCNTL_WORDR_MASK</a>&#160;&#160;&#160;0x00020000</td></tr>
<tr class="memdesc:ga05a3dd5b5ff4ddb1ed8bd33f091893d3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write Response Order Enable.  <a href="group__trafgen__v3__2.html#ga05a3dd5b5ff4ddb1ed8bd33f091893d3">More...</a><br /></td></tr>
<tr class="separator:ga05a3dd5b5ff4ddb1ed8bd33f091893d3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadd90aa32d6ffdb6c248aae48b4d03990"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gadd90aa32d6ffdb6c248aae48b4d03990">XTG_SCNTL_RORDR_MASK</a>&#160;&#160;&#160;0x00010000</td></tr>
<tr class="memdesc:gadd90aa32d6ffdb6c248aae48b4d03990"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read Response Order Enable.  <a href="group__trafgen__v3__2.html#gadd90aa32d6ffdb6c248aae48b4d03990">More...</a><br /></td></tr>
<tr class="separator:gadd90aa32d6ffdb6c248aae48b4d03990"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab3fd9e680a247d1ad78ba6cab9b061fb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gab3fd9e680a247d1ad78ba6cab9b061fb">XTG_SCNTL_ERREN_MASK</a>&#160;&#160;&#160;0x00008000</td></tr>
<tr class="memdesc:gab3fd9e680a247d1ad78ba6cab9b061fb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slv Error Interrupt Enable.  <a href="group__trafgen__v3__2.html#gab3fd9e680a247d1ad78ba6cab9b061fb">More...</a><br /></td></tr>
<tr class="separator:gab3fd9e680a247d1ad78ba6cab9b061fb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Error bitmasks</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are shared with the XTG_ERR_STS_OFFSET and XTG_ERR_EN_OFFSET register. </p>
</div></td></tr>
<tr class="memitem:ga7a6d5a7be767a9e7de7e441416584ba5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga7a6d5a7be767a9e7de7e441416584ba5">XTG_ERR_ALL_MSTERR_MASK</a>&#160;&#160;&#160;0x001F0000</td></tr>
<tr class="memdesc:ga7a6d5a7be767a9e7de7e441416584ba5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Master Errors Mask.  <a href="group__trafgen__v3__2.html#ga7a6d5a7be767a9e7de7e441416584ba5">More...</a><br /></td></tr>
<tr class="separator:ga7a6d5a7be767a9e7de7e441416584ba5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9c335dd2550acee9495bfd72fc7e3e4d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga9c335dd2550acee9495bfd72fc7e3e4d">XTG_ERR_ALL_SLVERR_MASK</a>&#160;&#160;&#160;0x00000003</td></tr>
<tr class="memdesc:ga9c335dd2550acee9495bfd72fc7e3e4d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave Errors Mask.  <a href="group__trafgen__v3__2.html#ga9c335dd2550acee9495bfd72fc7e3e4d">More...</a><br /></td></tr>
<tr class="separator:ga9c335dd2550acee9495bfd72fc7e3e4d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafdb598343bdb0bf2c6c5d29f8258f692"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gafdb598343bdb0bf2c6c5d29f8258f692">XTG_ERR_ALL_ERR_MASK</a>&#160;&#160;&#160;0x001F0003</td></tr>
<tr class="memdesc:gafdb598343bdb0bf2c6c5d29f8258f692"><td class="mdescLeft">&#160;</td><td class="mdescRight">All Errors Mask.  <a href="group__trafgen__v3__2.html#gafdb598343bdb0bf2c6c5d29f8258f692">More...</a><br /></td></tr>
<tr class="separator:gafdb598343bdb0bf2c6c5d29f8258f692"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5cefaef257524651df762212be509765"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga5cefaef257524651df762212be509765">XTG_ERR_MSTCMP_MASK</a>&#160;&#160;&#160;0x80000000</td></tr>
<tr class="memdesc:ga5cefaef257524651df762212be509765"><td class="mdescLeft">&#160;</td><td class="mdescRight">Master Complete Mask.  <a href="group__trafgen__v3__2.html#ga5cefaef257524651df762212be509765">More...</a><br /></td></tr>
<tr class="separator:ga5cefaef257524651df762212be509765"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf6d50ea72391faca9e9bf364ac16abbe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gaf6d50ea72391faca9e9bf364ac16abbe">XTG_ERR_RIDER_MASK</a>&#160;&#160;&#160;0x00100000</td></tr>
<tr class="memdesc:gaf6d50ea72391faca9e9bf364ac16abbe"><td class="mdescLeft">&#160;</td><td class="mdescRight">Master Invalid RVALID Mask.  <a href="group__trafgen__v3__2.html#gaf6d50ea72391faca9e9bf364ac16abbe">More...</a><br /></td></tr>
<tr class="separator:gaf6d50ea72391faca9e9bf364ac16abbe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga93be7e7fdaaa372c2b888c07ecfd6466"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga93be7e7fdaaa372c2b888c07ecfd6466">XTG_ERR_WIDER_MASK</a>&#160;&#160;&#160;0x00080000</td></tr>
<tr class="memdesc:ga93be7e7fdaaa372c2b888c07ecfd6466"><td class="mdescLeft">&#160;</td><td class="mdescRight">Master Invalid BVALID Mask.  <a href="group__trafgen__v3__2.html#ga93be7e7fdaaa372c2b888c07ecfd6466">More...</a><br /></td></tr>
<tr class="separator:ga93be7e7fdaaa372c2b888c07ecfd6466"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6e70386e2b3071efc1391dea0c6d7ff7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga6e70386e2b3071efc1391dea0c6d7ff7">XTG_ERR_WRSPER_MASK</a>&#160;&#160;&#160;0x00040000</td></tr>
<tr class="memdesc:ga6e70386e2b3071efc1391dea0c6d7ff7"><td class="mdescLeft">&#160;</td><td class="mdescRight">MW Invalid RESP Mask.  <a href="group__trafgen__v3__2.html#ga6e70386e2b3071efc1391dea0c6d7ff7">More...</a><br /></td></tr>
<tr class="separator:ga6e70386e2b3071efc1391dea0c6d7ff7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga40d2ed4ab43a43d5911d28db379536f9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga40d2ed4ab43a43d5911d28db379536f9">XTG_ERR_RERRSP_MASK</a>&#160;&#160;&#160;0x00020000</td></tr>
<tr class="memdesc:ga40d2ed4ab43a43d5911d28db379536f9"><td class="mdescLeft">&#160;</td><td class="mdescRight">MR Invalid RESP Mask.  <a href="group__trafgen__v3__2.html#ga40d2ed4ab43a43d5911d28db379536f9">More...</a><br /></td></tr>
<tr class="separator:ga40d2ed4ab43a43d5911d28db379536f9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad4008be388657e20fcb49511a5d38a3e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#gad4008be388657e20fcb49511a5d38a3e">XTG_ERR_RLENER_MASK</a>&#160;&#160;&#160;0x00010000</td></tr>
<tr class="memdesc:gad4008be388657e20fcb49511a5d38a3e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Master Read Length Mask.  <a href="group__trafgen__v3__2.html#gad4008be388657e20fcb49511a5d38a3e">More...</a><br /></td></tr>
<tr class="separator:gad4008be388657e20fcb49511a5d38a3e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9585c4a750db5e61e49ada2c30d2cc71"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga9585c4a750db5e61e49ada2c30d2cc71">XTG_ERR_SWSTRB_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:ga9585c4a750db5e61e49ada2c30d2cc71"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave WSTRB Illegal Mask.  <a href="group__trafgen__v3__2.html#ga9585c4a750db5e61e49ada2c30d2cc71">More...</a><br /></td></tr>
<tr class="separator:ga9585c4a750db5e61e49ada2c30d2cc71"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8f39b5d4a784a673cad5225ac1253f1b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__trafgen__v3__2.html#ga8f39b5d4a784a673cad5225ac1253f1b">XTG_ERR_SWLENER_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga8f39b5d4a784a673cad5225ac1253f1b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave Read Length Mask.  <a href="group__trafgen__v3__2.html#ga8f39b5d4a784a673cad5225ac1253f1b">More...</a><br /></td></tr>
<tr class="separator:ga8f39b5d4a784a673cad5225ac1253f1b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Master Error Interrupt Enable Register bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XTG_MSTERR_INTR_OFFSET register. </p>
</div></td></tr>
<tr class="memitem:a7f69f7e850cdf6eaeacb76be85d8ad51"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a7f69f7e850cdf6eaeacb76be85d8ad51">XTG_MSTERR_INTR_MINTREN_MASK</a>&#160;&#160;&#160;0x00008000</td></tr>
<tr class="memdesc:a7f69f7e850cdf6eaeacb76be85d8ad51"><td class="mdescLeft">&#160;</td><td class="mdescRight">Master Err Interrupt Enable.  <a href="#a7f69f7e850cdf6eaeacb76be85d8ad51">More...</a><br /></td></tr>
<tr class="separator:a7f69f7e850cdf6eaeacb76be85d8ad51"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Config Status Register bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XTG_CFG_STS_OFFSET register. </p>
</div></td></tr>
<tr class="memitem:a43010263c928054845a6e4da818c5cb6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a43010263c928054845a6e4da818c5cb6">XTG_CFG_STS_MWIDTH_SHIFT</a>&#160;&#160;&#160;28</td></tr>
<tr class="memdesc:a43010263c928054845a6e4da818c5cb6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Master Width Shift.  <a href="#a43010263c928054845a6e4da818c5cb6">More...</a><br /></td></tr>
<tr class="separator:a43010263c928054845a6e4da818c5cb6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7387f793b21568825291b8ae05e9a8dc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a7387f793b21568825291b8ae05e9a8dc">XTG_CFG_STS_MWIDTH_MASK</a>&#160;&#160;&#160;0x70000000</td></tr>
<tr class="memdesc:a7387f793b21568825291b8ae05e9a8dc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Master Width Mask.  <a href="#a7387f793b21568825291b8ae05e9a8dc">More...</a><br /></td></tr>
<tr class="separator:a7387f793b21568825291b8ae05e9a8dc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab8521be4a5dc1628cb3a3afe87298843"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#ab8521be4a5dc1628cb3a3afe87298843">XTG_CFG_STS_SWIDTH_SHIFT</a>&#160;&#160;&#160;25</td></tr>
<tr class="memdesc:ab8521be4a5dc1628cb3a3afe87298843"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave Width Shift.  <a href="#ab8521be4a5dc1628cb3a3afe87298843">More...</a><br /></td></tr>
<tr class="separator:ab8521be4a5dc1628cb3a3afe87298843"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a641638626484a52b81fbbf8f30bd45dc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a641638626484a52b81fbbf8f30bd45dc">XTG_CFG_STS_SWIDTH_MASK</a>&#160;&#160;&#160;0x0E000000</td></tr>
<tr class="memdesc:a641638626484a52b81fbbf8f30bd45dc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Slave Width Mask.  <a href="#a641638626484a52b81fbbf8f30bd45dc">More...</a><br /></td></tr>
<tr class="separator:a641638626484a52b81fbbf8f30bd45dc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1816012cab8ec1b93b06d20dde1e0128"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a1816012cab8ec1b93b06d20dde1e0128">XTG_CFG_STS_MFULL_MASK</a>&#160;&#160;&#160;0x01000000</td></tr>
<tr class="memdesc:a1816012cab8ec1b93b06d20dde1e0128"><td class="mdescLeft">&#160;</td><td class="mdescRight">Full Mode.  <a href="#a1816012cab8ec1b93b06d20dde1e0128">More...</a><br /></td></tr>
<tr class="separator:a1816012cab8ec1b93b06d20dde1e0128"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a73aac9edd6e776525f4e44865ed7e481"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a73aac9edd6e776525f4e44865ed7e481">XTG_CFG_STS_MBASIC_MASK</a>&#160;&#160;&#160;0x00800000</td></tr>
<tr class="memdesc:a73aac9edd6e776525f4e44865ed7e481"><td class="mdescLeft">&#160;</td><td class="mdescRight">Basic Mode.  <a href="#a73aac9edd6e776525f4e44865ed7e481">More...</a><br /></td></tr>
<tr class="separator:a73aac9edd6e776525f4e44865ed7e481"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Streaming Control Register bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XTG_STR_CFG_OFFSET register. </p>
</div></td></tr>
<tr class="memitem:a49c88fdab76f14bbf070eebcedc16ef1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a49c88fdab76f14bbf070eebcedc16ef1">XTG_STREAM_CNTL_VER_SHIFT</a>&#160;&#160;&#160;24</td></tr>
<tr class="memdesc:a49c88fdab76f14bbf070eebcedc16ef1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Version Shift.  <a href="#a49c88fdab76f14bbf070eebcedc16ef1">More...</a><br /></td></tr>
<tr class="separator:a49c88fdab76f14bbf070eebcedc16ef1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a33aba05b605e1929b2045d76228f04f5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a33aba05b605e1929b2045d76228f04f5">XTG_STREAM_CNTL_VER_MASK</a>&#160;&#160;&#160;0xFF000000</td></tr>
<tr class="memdesc:a33aba05b605e1929b2045d76228f04f5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Version Mask.  <a href="#a33aba05b605e1929b2045d76228f04f5">More...</a><br /></td></tr>
<tr class="separator:a33aba05b605e1929b2045d76228f04f5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3e492e71798bc4139c136551452503fa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a3e492e71798bc4139c136551452503fa">XTG_STREAM_CNTL_TD_SHIFT</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:a3e492e71798bc4139c136551452503fa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transfer Done Shift.  <a href="#a3e492e71798bc4139c136551452503fa">More...</a><br /></td></tr>
<tr class="separator:a3e492e71798bc4139c136551452503fa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4b0674a7c9f7879bf6462860641b4d89"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a4b0674a7c9f7879bf6462860641b4d89">XTG_STREAM_CNTL_TD_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:a4b0674a7c9f7879bf6462860641b4d89"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transfer Done Mask.  <a href="#a4b0674a7c9f7879bf6462860641b4d89">More...</a><br /></td></tr>
<tr class="separator:a4b0674a7c9f7879bf6462860641b4d89"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a96e6916449a1ded46ea7882b67d2d732"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a96e6916449a1ded46ea7882b67d2d732">XTG_STREAM_CNTL_STEN_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:a96e6916449a1ded46ea7882b67d2d732"><td class="mdescLeft">&#160;</td><td class="mdescRight">Streaming Enable Mask.  <a href="#a96e6916449a1ded46ea7882b67d2d732">More...</a><br /></td></tr>
<tr class="separator:a96e6916449a1ded46ea7882b67d2d732"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad4ac7a7ef3c84748869c001e04d5dade"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#ad4ac7a7ef3c84748869c001e04d5dade">XTG_STREAM_CNTL_RESET_MASK</a>&#160;&#160;&#160;0x00000000</td></tr>
<tr class="memdesc:ad4ac7a7ef3c84748869c001e04d5dade"><td class="mdescLeft">&#160;</td><td class="mdescRight">Streaming Disable Mask.  <a href="#ad4ac7a7ef3c84748869c001e04d5dade">More...</a><br /></td></tr>
<tr class="separator:ad4ac7a7ef3c84748869c001e04d5dade"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Streaming Config Register bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XTG_STR_CFG_OFFSET register. </p>
</div></td></tr>
<tr class="memitem:aea7d215adbbf69b18fac485e2d150bd9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#aea7d215adbbf69b18fac485e2d150bd9">XTG_STREAM_CFG_PDLY_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:aea7d215adbbf69b18fac485e2d150bd9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Programmable Delay Shift.  <a href="#aea7d215adbbf69b18fac485e2d150bd9">More...</a><br /></td></tr>
<tr class="separator:aea7d215adbbf69b18fac485e2d150bd9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a490ccc5cf897e6daf0e403fdb5028cc8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a490ccc5cf897e6daf0e403fdb5028cc8">XTG_STREAM_CFG_PDLY_MASK</a>&#160;&#160;&#160;0xFFFF0000</td></tr>
<tr class="memdesc:a490ccc5cf897e6daf0e403fdb5028cc8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Programmable Delay Mask.  <a href="#a490ccc5cf897e6daf0e403fdb5028cc8">More...</a><br /></td></tr>
<tr class="separator:a490ccc5cf897e6daf0e403fdb5028cc8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acf47f8d5a9f92da3d0d5b4fd6be627a6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#acf47f8d5a9f92da3d0d5b4fd6be627a6">XTG_STREAM_CFG_TDEST_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:acf47f8d5a9f92da3d0d5b4fd6be627a6"><td class="mdescLeft">&#160;</td><td class="mdescRight">TDEST PORT Shift.  <a href="#acf47f8d5a9f92da3d0d5b4fd6be627a6">More...</a><br /></td></tr>
<tr class="separator:acf47f8d5a9f92da3d0d5b4fd6be627a6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a27be0cf2c90513010b73b0b8db1163dc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a27be0cf2c90513010b73b0b8db1163dc">XTG_STREAM_CFG_TDEST_MASK</a>&#160;&#160;&#160;0x0000FF00</td></tr>
<tr class="memdesc:a27be0cf2c90513010b73b0b8db1163dc"><td class="mdescLeft">&#160;</td><td class="mdescRight">TDEST PORT Mask.  <a href="#a27be0cf2c90513010b73b0b8db1163dc">More...</a><br /></td></tr>
<tr class="separator:a27be0cf2c90513010b73b0b8db1163dc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae0436a212983ec018bba1d0a4352f32f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#ae0436a212983ec018bba1d0a4352f32f">XTG_STREAM_CFG_RANDLY_SHIFT</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:ae0436a212983ec018bba1d0a4352f32f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Random Delay Shift.  <a href="#ae0436a212983ec018bba1d0a4352f32f">More...</a><br /></td></tr>
<tr class="separator:ae0436a212983ec018bba1d0a4352f32f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae6da854602744d63b3fe0dfdc2dc22f9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#ae6da854602744d63b3fe0dfdc2dc22f9">XTG_STREAM_CFG_RANDLY_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:ae6da854602744d63b3fe0dfdc2dc22f9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Random Delay Mask.  <a href="#ae6da854602744d63b3fe0dfdc2dc22f9">More...</a><br /></td></tr>
<tr class="separator:ae6da854602744d63b3fe0dfdc2dc22f9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae44681fc73afbcdb7ae0015719f8ac47"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#ae44681fc73afbcdb7ae0015719f8ac47">XTG_STREAM_CFG_RANDL_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ae44681fc73afbcdb7ae0015719f8ac47"><td class="mdescLeft">&#160;</td><td class="mdescRight">Random Length Mask.  <a href="#ae44681fc73afbcdb7ae0015719f8ac47">More...</a><br /></td></tr>
<tr class="separator:ae44681fc73afbcdb7ae0015719f8ac47"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Streaming Transfer Length Register bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XTG_STR_TL_OFFSET register. </p>
</div></td></tr>
<tr class="memitem:a826017ee56ef1171a4d132dc12ca8341"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a826017ee56ef1171a4d132dc12ca8341">XTG_STREAM_TL_TCNT_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:a826017ee56ef1171a4d132dc12ca8341"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transfer Count Shift.  <a href="#a826017ee56ef1171a4d132dc12ca8341">More...</a><br /></td></tr>
<tr class="separator:a826017ee56ef1171a4d132dc12ca8341"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a556bcb7b08d4170167ee65c08c7a0ebe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a556bcb7b08d4170167ee65c08c7a0ebe">XTG_STREAM_TL_TCNT_MASK</a>&#160;&#160;&#160;0xFFFF0000</td></tr>
<tr class="memdesc:a556bcb7b08d4170167ee65c08c7a0ebe"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transfer Count Mask.  <a href="#a556bcb7b08d4170167ee65c08c7a0ebe">More...</a><br /></td></tr>
<tr class="separator:a556bcb7b08d4170167ee65c08c7a0ebe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae28f53acd7ef1f38265f560c17c64800"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#ae28f53acd7ef1f38265f560c17c64800">XTG_STREAM_TL_TLEN_MASK</a>&#160;&#160;&#160;0x0000FFFF</td></tr>
<tr class="memdesc:ae28f53acd7ef1f38265f560c17c64800"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transfer Length Mask.  <a href="#ae28f53acd7ef1f38265f560c17c64800">More...</a><br /></td></tr>
<tr class="separator:ae28f53acd7ef1f38265f560c17c64800"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Static Control Register bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XTG_STATIC_CNTL_OFFSET register. </p>
</div></td></tr>
<tr class="memitem:a128106d0d3435137e96192b0386eeec4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a128106d0d3435137e96192b0386eeec4">XTG_STATIC_CNTL_VER_SHIFT</a>&#160;&#160;&#160;24</td></tr>
<tr class="memdesc:a128106d0d3435137e96192b0386eeec4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Version Shift.  <a href="#a128106d0d3435137e96192b0386eeec4">More...</a><br /></td></tr>
<tr class="separator:a128106d0d3435137e96192b0386eeec4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2f470f08ec693fff5af6c5109f1b3ffc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a2f470f08ec693fff5af6c5109f1b3ffc">XTG_STATIC_CNTL_VER_MASK</a>&#160;&#160;&#160;0xFF000000</td></tr>
<tr class="memdesc:a2f470f08ec693fff5af6c5109f1b3ffc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Version Mask.  <a href="#a2f470f08ec693fff5af6c5109f1b3ffc">More...</a><br /></td></tr>
<tr class="separator:a2f470f08ec693fff5af6c5109f1b3ffc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac0e75db08cd3774207a38bdfe78f2ac9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#ac0e75db08cd3774207a38bdfe78f2ac9">XTG_STATIC_CNTL_TD_SHIFT</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:ac0e75db08cd3774207a38bdfe78f2ac9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transfer Done Shift.  <a href="#ac0e75db08cd3774207a38bdfe78f2ac9">More...</a><br /></td></tr>
<tr class="separator:ac0e75db08cd3774207a38bdfe78f2ac9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae82296e2d81edb5da14c813e36b604cc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#ae82296e2d81edb5da14c813e36b604cc">XTG_STATIC_CNTL_TD_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:ae82296e2d81edb5da14c813e36b604cc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transfer Done Mask.  <a href="#ae82296e2d81edb5da14c813e36b604cc">More...</a><br /></td></tr>
<tr class="separator:ae82296e2d81edb5da14c813e36b604cc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a820c08467cb0fc69af91e8747bf52199"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a820c08467cb0fc69af91e8747bf52199">XTG_STATIC_CNTL_STEN_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:a820c08467cb0fc69af91e8747bf52199"><td class="mdescLeft">&#160;</td><td class="mdescRight">Static enable Mask.  <a href="#a820c08467cb0fc69af91e8747bf52199">More...</a><br /></td></tr>
<tr class="separator:a820c08467cb0fc69af91e8747bf52199"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4955ccf9832cc09dd5f05b54f49104dd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a4955ccf9832cc09dd5f05b54f49104dd">XTG_STATIC_CNTL_RESET_MASK</a>&#160;&#160;&#160;0x00000000</td></tr>
<tr class="memdesc:a4955ccf9832cc09dd5f05b54f49104dd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Static Disable Mask.  <a href="#a4955ccf9832cc09dd5f05b54f49104dd">More...</a><br /></td></tr>
<tr class="separator:a4955ccf9832cc09dd5f05b54f49104dd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Static Length Register bit definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These bits are associated with the XTG_STATIC_LEN_OFFSET register. </p>
</div></td></tr>
<tr class="memitem:a6a65cb71fdd0717246547dbbe16b6e1b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a6a65cb71fdd0717246547dbbe16b6e1b">XTG_STATIC_LEN_BLEN_MASK</a>&#160;&#160;&#160;0x000000FF</td></tr>
<tr class="memdesc:a6a65cb71fdd0717246547dbbe16b6e1b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Burst length Mask.  <a href="#a6a65cb71fdd0717246547dbbe16b6e1b">More...</a><br /></td></tr>
<tr class="separator:a6a65cb71fdd0717246547dbbe16b6e1b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Axi Traffic Generator Command Entry field mask/shifts</div></td></tr>
<tr class="memitem:a575795d7d5b2348195e02fd8cccabe39"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a575795d7d5b2348195e02fd8cccabe39">XTG_ADDR_MASK</a>&#160;&#160;&#160;0xFFFFFFFF</td></tr>
<tr class="memdesc:a575795d7d5b2348195e02fd8cccabe39"><td class="mdescLeft">&#160;</td><td class="mdescRight">Driven to a*_addr line.  <a href="#a575795d7d5b2348195e02fd8cccabe39">More...</a><br /></td></tr>
<tr class="separator:a575795d7d5b2348195e02fd8cccabe39"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a74fdcca6bba8dfbfd0ed288f9132bab0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a74fdcca6bba8dfbfd0ed288f9132bab0">XTG_LEN_MASK</a>&#160;&#160;&#160;0xFF</td></tr>
<tr class="memdesc:a74fdcca6bba8dfbfd0ed288f9132bab0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Driven to a*_len line.  <a href="#a74fdcca6bba8dfbfd0ed288f9132bab0">More...</a><br /></td></tr>
<tr class="separator:a74fdcca6bba8dfbfd0ed288f9132bab0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6575f2dffb01e56c6b38eda8190664b8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a6575f2dffb01e56c6b38eda8190664b8">XTG_LOCK_MASK</a>&#160;&#160;&#160;0x1</td></tr>
<tr class="memdesc:a6575f2dffb01e56c6b38eda8190664b8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Driven to a*_lock line.  <a href="#a6575f2dffb01e56c6b38eda8190664b8">More...</a><br /></td></tr>
<tr class="separator:a6575f2dffb01e56c6b38eda8190664b8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae149dfc387f997a33cbe70d57362fc0f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#ae149dfc387f997a33cbe70d57362fc0f">XTG_BURST_MASK</a>&#160;&#160;&#160;0x3</td></tr>
<tr class="memdesc:ae149dfc387f997a33cbe70d57362fc0f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Driven to a*_burst line.  <a href="#ae149dfc387f997a33cbe70d57362fc0f">More...</a><br /></td></tr>
<tr class="separator:ae149dfc387f997a33cbe70d57362fc0f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acba37550ee94c7c7022aa5a3ad946fc3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#acba37550ee94c7c7022aa5a3ad946fc3">XTG_SIZE_MASK</a>&#160;&#160;&#160;0x7</td></tr>
<tr class="memdesc:acba37550ee94c7c7022aa5a3ad946fc3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Driven to a*_size line.  <a href="#acba37550ee94c7c7022aa5a3ad946fc3">More...</a><br /></td></tr>
<tr class="separator:acba37550ee94c7c7022aa5a3ad946fc3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5a7178fbdfb4b46aaa7bd0fc308ec636"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a5a7178fbdfb4b46aaa7bd0fc308ec636">XTG_ID_MASK</a>&#160;&#160;&#160;0x3F</td></tr>
<tr class="memdesc:a5a7178fbdfb4b46aaa7bd0fc308ec636"><td class="mdescLeft">&#160;</td><td class="mdescRight">Driven to a*_id line.  <a href="#a5a7178fbdfb4b46aaa7bd0fc308ec636">More...</a><br /></td></tr>
<tr class="separator:a5a7178fbdfb4b46aaa7bd0fc308ec636"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae6b714a335a4b02967a37f0ead14508a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#ae6b714a335a4b02967a37f0ead14508a">XTG_PROT_MASK</a>&#160;&#160;&#160;0x7</td></tr>
<tr class="memdesc:ae6b714a335a4b02967a37f0ead14508a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Driven to a*_prot line.  <a href="#ae6b714a335a4b02967a37f0ead14508a">More...</a><br /></td></tr>
<tr class="separator:ae6b714a335a4b02967a37f0ead14508a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9267c6248c021a02be574f803f11c677"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a9267c6248c021a02be574f803f11c677">XTG_LAST_ADDR_MASK</a>&#160;&#160;&#160;0x7</td></tr>
<tr class="memdesc:a9267c6248c021a02be574f803f11c677"><td class="mdescLeft">&#160;</td><td class="mdescRight">Last address.  <a href="#a9267c6248c021a02be574f803f11c677">More...</a><br /></td></tr>
<tr class="separator:a9267c6248c021a02be574f803f11c677"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a584b02e4845e493b2854d3c865aaed19"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a584b02e4845e493b2854d3c865aaed19">XTG_VALID_CMD_MASK</a>&#160;&#160;&#160;0x1</td></tr>
<tr class="memdesc:a584b02e4845e493b2854d3c865aaed19"><td class="mdescLeft">&#160;</td><td class="mdescRight">Valid Command.  <a href="#a584b02e4845e493b2854d3c865aaed19">More...</a><br /></td></tr>
<tr class="separator:a584b02e4845e493b2854d3c865aaed19"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae797ad9c3446d0523af686f5a1360a2e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#ae797ad9c3446d0523af686f5a1360a2e">XTG_MSTRAM_INDEX_MASK</a>&#160;&#160;&#160;0x1FFF</td></tr>
<tr class="memdesc:ae797ad9c3446d0523af686f5a1360a2e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Master RAM Index.  <a href="#ae797ad9c3446d0523af686f5a1360a2e">More...</a><br /></td></tr>
<tr class="separator:ae797ad9c3446d0523af686f5a1360a2e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a50464785b101e677032e4956a4592a0e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a50464785b101e677032e4956a4592a0e">XTG_OTHER_DEPEND_MASK</a>&#160;&#160;&#160;0x1FF</td></tr>
<tr class="memdesc:a50464785b101e677032e4956a4592a0e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Other depend Command no.  <a href="#a50464785b101e677032e4956a4592a0e">More...</a><br /></td></tr>
<tr class="separator:a50464785b101e677032e4956a4592a0e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a23937f160c785883f46e3e8ac03af193"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a23937f160c785883f46e3e8ac03af193">XTG_MY_DEPEND_MASK</a>&#160;&#160;&#160;0x1FF</td></tr>
<tr class="memdesc:a23937f160c785883f46e3e8ac03af193"><td class="mdescLeft">&#160;</td><td class="mdescRight">My depend command no.  <a href="#a23937f160c785883f46e3e8ac03af193">More...</a><br /></td></tr>
<tr class="separator:a23937f160c785883f46e3e8ac03af193"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a31f414339e85047271ed193829b066b6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a31f414339e85047271ed193829b066b6">XTG_QOS_MASK</a>&#160;&#160;&#160;0xF</td></tr>
<tr class="memdesc:a31f414339e85047271ed193829b066b6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Driven to a*_qos line.  <a href="#a31f414339e85047271ed193829b066b6">More...</a><br /></td></tr>
<tr class="separator:a31f414339e85047271ed193829b066b6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6dda4f385ddd7962f4b7978fc1c42664"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a6dda4f385ddd7962f4b7978fc1c42664">XTG_USER_MASK</a>&#160;&#160;&#160;0xFF</td></tr>
<tr class="memdesc:a6dda4f385ddd7962f4b7978fc1c42664"><td class="mdescLeft">&#160;</td><td class="mdescRight">Driven to a*_user line.  <a href="#a6dda4f385ddd7962f4b7978fc1c42664">More...</a><br /></td></tr>
<tr class="separator:a6dda4f385ddd7962f4b7978fc1c42664"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3b4631d92345fd27ee3e40d827a184f3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a3b4631d92345fd27ee3e40d827a184f3">XTG_CACHE_MASK</a>&#160;&#160;&#160;0xF</td></tr>
<tr class="memdesc:a3b4631d92345fd27ee3e40d827a184f3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Driven to a*_cache line.  <a href="#a3b4631d92345fd27ee3e40d827a184f3">More...</a><br /></td></tr>
<tr class="separator:a3b4631d92345fd27ee3e40d827a184f3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad893dd4b8011e14e68b21afa20c019c8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#ad893dd4b8011e14e68b21afa20c019c8">XTG_EXPECTED_RESP_MASK</a>&#160;&#160;&#160;0x7</td></tr>
<tr class="memdesc:ad893dd4b8011e14e68b21afa20c019c8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Expected response.  <a href="#ad893dd4b8011e14e68b21afa20c019c8">More...</a><br /></td></tr>
<tr class="separator:ad893dd4b8011e14e68b21afa20c019c8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4fec29a2aedb84ed9410fe5298245d24"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a4fec29a2aedb84ed9410fe5298245d24">XTG_ADDR_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:a4fec29a2aedb84ed9410fe5298245d24"><td class="mdescLeft">&#160;</td><td class="mdescRight">Driven to a*_addr line.  <a href="#a4fec29a2aedb84ed9410fe5298245d24">More...</a><br /></td></tr>
<tr class="separator:a4fec29a2aedb84ed9410fe5298245d24"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae25779b53195ced1e45d64bc53344c28"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#ae25779b53195ced1e45d64bc53344c28">XTG_LEN_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ae25779b53195ced1e45d64bc53344c28"><td class="mdescLeft">&#160;</td><td class="mdescRight">Driven to a*_len line.  <a href="#ae25779b53195ced1e45d64bc53344c28">More...</a><br /></td></tr>
<tr class="separator:ae25779b53195ced1e45d64bc53344c28"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a819696f324a87fbdf9dbce5c6aafcdaf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a819696f324a87fbdf9dbce5c6aafcdaf">XTG_LOCK_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:a819696f324a87fbdf9dbce5c6aafcdaf"><td class="mdescLeft">&#160;</td><td class="mdescRight">Driven to a*_lock line.  <a href="#a819696f324a87fbdf9dbce5c6aafcdaf">More...</a><br /></td></tr>
<tr class="separator:a819696f324a87fbdf9dbce5c6aafcdaf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a70414e4d0c831df19899fe7c050a7a03"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a70414e4d0c831df19899fe7c050a7a03">XTG_BURST_SHIFT</a>&#160;&#160;&#160;10</td></tr>
<tr class="memdesc:a70414e4d0c831df19899fe7c050a7a03"><td class="mdescLeft">&#160;</td><td class="mdescRight">Driven to a*_burst line.  <a href="#a70414e4d0c831df19899fe7c050a7a03">More...</a><br /></td></tr>
<tr class="separator:a70414e4d0c831df19899fe7c050a7a03"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6523ef7f08423cbc5150e3d6e55abd99"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a6523ef7f08423cbc5150e3d6e55abd99">XTG_SIZE_SHIFT</a>&#160;&#160;&#160;12</td></tr>
<tr class="memdesc:a6523ef7f08423cbc5150e3d6e55abd99"><td class="mdescLeft">&#160;</td><td class="mdescRight">Driven to a*_size line.  <a href="#a6523ef7f08423cbc5150e3d6e55abd99">More...</a><br /></td></tr>
<tr class="separator:a6523ef7f08423cbc5150e3d6e55abd99"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abf8893d48139c874e7628a7d32d1861b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#abf8893d48139c874e7628a7d32d1861b">XTG_ID_SHIFT</a>&#160;&#160;&#160;15</td></tr>
<tr class="memdesc:abf8893d48139c874e7628a7d32d1861b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Driven to a*_id line.  <a href="#abf8893d48139c874e7628a7d32d1861b">More...</a><br /></td></tr>
<tr class="separator:abf8893d48139c874e7628a7d32d1861b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0796a27df8444fd763ccd6c0356aa8e4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a0796a27df8444fd763ccd6c0356aa8e4">XTG_PROT_SHIFT</a>&#160;&#160;&#160;21</td></tr>
<tr class="memdesc:a0796a27df8444fd763ccd6c0356aa8e4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Driven to a*_prot line.  <a href="#a0796a27df8444fd763ccd6c0356aa8e4">More...</a><br /></td></tr>
<tr class="separator:a0796a27df8444fd763ccd6c0356aa8e4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab2e214bbd75cfa106a9cf34a075ca7c3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#ab2e214bbd75cfa106a9cf34a075ca7c3">XTG_LAST_ADDR_SHIFT</a>&#160;&#160;&#160;28</td></tr>
<tr class="memdesc:ab2e214bbd75cfa106a9cf34a075ca7c3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Last address.  <a href="#ab2e214bbd75cfa106a9cf34a075ca7c3">More...</a><br /></td></tr>
<tr class="separator:ab2e214bbd75cfa106a9cf34a075ca7c3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4387f942768e60fd471499c63ad5e7dd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a4387f942768e60fd471499c63ad5e7dd">XTG_VALID_CMD_SHIFT</a>&#160;&#160;&#160;31</td></tr>
<tr class="memdesc:a4387f942768e60fd471499c63ad5e7dd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Valid Command.  <a href="#a4387f942768e60fd471499c63ad5e7dd">More...</a><br /></td></tr>
<tr class="separator:a4387f942768e60fd471499c63ad5e7dd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adac26542aa0ea0c464a48d0c60086788"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#adac26542aa0ea0c464a48d0c60086788">XTG_MSTRAM_INDEX_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:adac26542aa0ea0c464a48d0c60086788"><td class="mdescLeft">&#160;</td><td class="mdescRight">Master RAM Index.  <a href="#adac26542aa0ea0c464a48d0c60086788">More...</a><br /></td></tr>
<tr class="separator:adac26542aa0ea0c464a48d0c60086788"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a18b2f14ba07703fe0e078d326496231d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a18b2f14ba07703fe0e078d326496231d">XTG_OTHER_DEPEND_SHIFT</a>&#160;&#160;&#160;13</td></tr>
<tr class="memdesc:a18b2f14ba07703fe0e078d326496231d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Other depend cmd num.  <a href="#a18b2f14ba07703fe0e078d326496231d">More...</a><br /></td></tr>
<tr class="separator:a18b2f14ba07703fe0e078d326496231d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a43673c92101ad1d1af680384add5f610"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a43673c92101ad1d1af680384add5f610">XTG_MY_DEPEND_SHIFT</a>&#160;&#160;&#160;22</td></tr>
<tr class="memdesc:a43673c92101ad1d1af680384add5f610"><td class="mdescLeft">&#160;</td><td class="mdescRight">My depend cmd num.  <a href="#a43673c92101ad1d1af680384add5f610">More...</a><br /></td></tr>
<tr class="separator:a43673c92101ad1d1af680384add5f610"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae3f2ee00c71bc8f847738acf83bf1c5c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#ae3f2ee00c71bc8f847738acf83bf1c5c">XTG_QOS_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:ae3f2ee00c71bc8f847738acf83bf1c5c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Driven to a*_qos line.  <a href="#ae3f2ee00c71bc8f847738acf83bf1c5c">More...</a><br /></td></tr>
<tr class="separator:ae3f2ee00c71bc8f847738acf83bf1c5c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a280ef09f695b10f97848ce74d68f7c02"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a280ef09f695b10f97848ce74d68f7c02">XTG_USER_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:a280ef09f695b10f97848ce74d68f7c02"><td class="mdescLeft">&#160;</td><td class="mdescRight">Driven to a*_user line.  <a href="#a280ef09f695b10f97848ce74d68f7c02">More...</a><br /></td></tr>
<tr class="separator:a280ef09f695b10f97848ce74d68f7c02"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6496641578aa8a7a22dd3c6147221175"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a6496641578aa8a7a22dd3c6147221175">XTG_CACHE_SHIFT</a>&#160;&#160;&#160;4</td></tr>
<tr class="memdesc:a6496641578aa8a7a22dd3c6147221175"><td class="mdescLeft">&#160;</td><td class="mdescRight">Driven to a*_cache line.  <a href="#a6496641578aa8a7a22dd3c6147221175">More...</a><br /></td></tr>
<tr class="separator:a6496641578aa8a7a22dd3c6147221175"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abc9721f5268f2b05074b669d5603b1e7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#abc9721f5268f2b05074b669d5603b1e7">XTG_EXPECTED_RESP_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:abc9721f5268f2b05074b669d5603b1e7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Expected response.  <a href="#abc9721f5268f2b05074b669d5603b1e7">More...</a><br /></td></tr>
<tr class="separator:abc9721f5268f2b05074b669d5603b1e7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Axi Traffic Generator Parameter Entry field mask/shifts</div></td></tr>
<tr class="memitem:a428fb28a58206c20a2bda291fd8966a4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a428fb28a58206c20a2bda291fd8966a4">XTG_PARAM_ADDRMODE_SHIFT</a>&#160;&#160;&#160;24</td></tr>
<tr class="memdesc:a428fb28a58206c20a2bda291fd8966a4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Address mode.  <a href="#a428fb28a58206c20a2bda291fd8966a4">More...</a><br /></td></tr>
<tr class="separator:a428fb28a58206c20a2bda291fd8966a4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac10bb6f9809e4f577bd36cb5dde0354e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#ac10bb6f9809e4f577bd36cb5dde0354e">XTG_PARAM_INTERVALMODE_SHIFT</a>&#160;&#160;&#160;26</td></tr>
<tr class="memdesc:ac10bb6f9809e4f577bd36cb5dde0354e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interval mode.  <a href="#ac10bb6f9809e4f577bd36cb5dde0354e">More...</a><br /></td></tr>
<tr class="separator:ac10bb6f9809e4f577bd36cb5dde0354e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adf334f6bf0852006382b697cc4ab59ce"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#adf334f6bf0852006382b697cc4ab59ce">XTG_PARAM_IDMODE_SHIFT</a>&#160;&#160;&#160;28</td></tr>
<tr class="memdesc:adf334f6bf0852006382b697cc4ab59ce"><td class="mdescLeft">&#160;</td><td class="mdescRight">Id mode.  <a href="#adf334f6bf0852006382b697cc4ab59ce">More...</a><br /></td></tr>
<tr class="separator:adf334f6bf0852006382b697cc4ab59ce"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a120a164368673bb038500e599e1501ea"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a120a164368673bb038500e599e1501ea">XTG_PARAM_OP_SHIFT</a>&#160;&#160;&#160;29</td></tr>
<tr class="memdesc:a120a164368673bb038500e599e1501ea"><td class="mdescLeft">&#160;</td><td class="mdescRight">Opcode.  <a href="#a120a164368673bb038500e599e1501ea">More...</a><br /></td></tr>
<tr class="separator:a120a164368673bb038500e599e1501ea"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aec8150e49af318bfd447d9b3cbf80734"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#aec8150e49af318bfd447d9b3cbf80734">XTG_PARAM_COUNT_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:aec8150e49af318bfd447d9b3cbf80734"><td class="mdescLeft">&#160;</td><td class="mdescRight">Repeat/Delay count.  <a href="#aec8150e49af318bfd447d9b3cbf80734">More...</a><br /></td></tr>
<tr class="separator:aec8150e49af318bfd447d9b3cbf80734"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a67d17cf7158e597c2307e21521e35812"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a67d17cf7158e597c2307e21521e35812">XTG_PARAM_DELAYRANGE_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:a67d17cf7158e597c2307e21521e35812"><td class="mdescLeft">&#160;</td><td class="mdescRight">Delay Range.  <a href="#a67d17cf7158e597c2307e21521e35812">More...</a><br /></td></tr>
<tr class="separator:a67d17cf7158e597c2307e21521e35812"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afd5037cc1466de72917fbcdd8c87e784"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#afd5037cc1466de72917fbcdd8c87e784">XTG_PARAM_DELAY_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:afd5037cc1466de72917fbcdd8c87e784"><td class="mdescLeft">&#160;</td><td class="mdescRight">FIXED RPT Delay count.  <a href="#afd5037cc1466de72917fbcdd8c87e784">More...</a><br /></td></tr>
<tr class="separator:afd5037cc1466de72917fbcdd8c87e784"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0ecc1e7486d1e09d8e771674e163e215"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a0ecc1e7486d1e09d8e771674e163e215">XTG_PARAM_ADDRRANGE_SHIFT</a>&#160;&#160;&#160;20</td></tr>
<tr class="memdesc:a0ecc1e7486d1e09d8e771674e163e215"><td class="mdescLeft">&#160;</td><td class="mdescRight">Address Range.  <a href="#a0ecc1e7486d1e09d8e771674e163e215">More...</a><br /></td></tr>
<tr class="separator:a0ecc1e7486d1e09d8e771674e163e215"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1db016038b97b33a8f6ac84a1aeb9b05"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a1db016038b97b33a8f6ac84a1aeb9b05">XTG_PARAM_ADDRMODE_MASK</a>&#160;&#160;&#160;0x3</td></tr>
<tr class="memdesc:a1db016038b97b33a8f6ac84a1aeb9b05"><td class="mdescLeft">&#160;</td><td class="mdescRight">Address mode.  <a href="#a1db016038b97b33a8f6ac84a1aeb9b05">More...</a><br /></td></tr>
<tr class="separator:a1db016038b97b33a8f6ac84a1aeb9b05"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5e5c93dc4a415adb31056d163fff03db"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a5e5c93dc4a415adb31056d163fff03db">XTG_PARAM_INTERVALMODE_MASK</a>&#160;&#160;&#160;0x3</td></tr>
<tr class="memdesc:a5e5c93dc4a415adb31056d163fff03db"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interval mode.  <a href="#a5e5c93dc4a415adb31056d163fff03db">More...</a><br /></td></tr>
<tr class="separator:a5e5c93dc4a415adb31056d163fff03db"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7358e0b257a66c3dea934297d4ce2e4c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a7358e0b257a66c3dea934297d4ce2e4c">XTG_PARAM_IDMODE_MASK</a>&#160;&#160;&#160;0x1</td></tr>
<tr class="memdesc:a7358e0b257a66c3dea934297d4ce2e4c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Id mode.  <a href="#a7358e0b257a66c3dea934297d4ce2e4c">More...</a><br /></td></tr>
<tr class="separator:a7358e0b257a66c3dea934297d4ce2e4c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a65d8f9067f4a40826da17eca055cac9e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a65d8f9067f4a40826da17eca055cac9e">XTG_PARAM_OP_MASK</a>&#160;&#160;&#160;0x7</td></tr>
<tr class="memdesc:a65d8f9067f4a40826da17eca055cac9e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Opcode.  <a href="#a65d8f9067f4a40826da17eca055cac9e">More...</a><br /></td></tr>
<tr class="separator:a65d8f9067f4a40826da17eca055cac9e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab433ce1c62131e78ac0d5376c85cfeab"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#ab433ce1c62131e78ac0d5376c85cfeab">XTG_PARAM_COUNT_MASK</a>&#160;&#160;&#160;0xFFFFFF</td></tr>
<tr class="memdesc:ab433ce1c62131e78ac0d5376c85cfeab"><td class="mdescLeft">&#160;</td><td class="mdescRight">Repeat/Delay count.  <a href="#ab433ce1c62131e78ac0d5376c85cfeab">More...</a><br /></td></tr>
<tr class="separator:ab433ce1c62131e78ac0d5376c85cfeab"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae2ffe39b97ed925d219f1abb0ce23916"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#ae2ffe39b97ed925d219f1abb0ce23916">XTG_PARAM_DELAYRANGE_MASK</a>&#160;&#160;&#160;0xFF</td></tr>
<tr class="memdesc:ae2ffe39b97ed925d219f1abb0ce23916"><td class="mdescLeft">&#160;</td><td class="mdescRight">Delay Range.  <a href="#ae2ffe39b97ed925d219f1abb0ce23916">More...</a><br /></td></tr>
<tr class="separator:ae2ffe39b97ed925d219f1abb0ce23916"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad8b0023a1d6151920452773820e2e1a0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#ad8b0023a1d6151920452773820e2e1a0">XTG_PARAM_DELAY_MASK</a>&#160;&#160;&#160;0xFFF</td></tr>
<tr class="memdesc:ad8b0023a1d6151920452773820e2e1a0"><td class="mdescLeft">&#160;</td><td class="mdescRight">FIXED RPT Delay count.  <a href="#ad8b0023a1d6151920452773820e2e1a0">More...</a><br /></td></tr>
<tr class="separator:ad8b0023a1d6151920452773820e2e1a0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a04045088459eca529c1dc34dccdcc889"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a04045088459eca529c1dc34dccdcc889">XTG_PARAM_ADDRRANGE_MASK</a>&#160;&#160;&#160;0xF</td></tr>
<tr class="memdesc:a04045088459eca529c1dc34dccdcc889"><td class="mdescLeft">&#160;</td><td class="mdescRight">Address Range.  <a href="#a04045088459eca529c1dc34dccdcc889">More...</a><br /></td></tr>
<tr class="separator:a04045088459eca529c1dc34dccdcc889"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a71baeb60d7cd7baa527e7d87378632c0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a71baeb60d7cd7baa527e7d87378632c0">XTG_PARAM_OP_NOP</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:a71baeb60d7cd7baa527e7d87378632c0"><td class="mdescLeft">&#160;</td><td class="mdescRight">NOP mode.  <a href="#a71baeb60d7cd7baa527e7d87378632c0">More...</a><br /></td></tr>
<tr class="separator:a71baeb60d7cd7baa527e7d87378632c0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad4415c801c23c948e6c180ad252e0d8f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#ad4415c801c23c948e6c180ad252e0d8f">XTG_PARAM_OP_RPT</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:ad4415c801c23c948e6c180ad252e0d8f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Repeat mode.  <a href="#ad4415c801c23c948e6c180ad252e0d8f">More...</a><br /></td></tr>
<tr class="separator:ad4415c801c23c948e6c180ad252e0d8f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a888fa5e45c08153523c902eacb4078a8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a888fa5e45c08153523c902eacb4078a8">XTG_PARAM_OP_DELAY</a>&#160;&#160;&#160;2</td></tr>
<tr class="memdesc:a888fa5e45c08153523c902eacb4078a8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Delay mode.  <a href="#a888fa5e45c08153523c902eacb4078a8">More...</a><br /></td></tr>
<tr class="separator:a888fa5e45c08153523c902eacb4078a8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a64bfe0cfa6be21facf834f5d49c2a706"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a64bfe0cfa6be21facf834f5d49c2a706">XTG_PARAM_OP_FIXEDRPT</a>&#160;&#160;&#160;3</td></tr>
<tr class="memdesc:a64bfe0cfa6be21facf834f5d49c2a706"><td class="mdescLeft">&#160;</td><td class="mdescRight">Fixed Repeat Delay.  <a href="#a64bfe0cfa6be21facf834f5d49c2a706">More...</a><br /></td></tr>
<tr class="separator:a64bfe0cfa6be21facf834f5d49c2a706"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa9eeb814676b06669a3e4fe310717efe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#aa9eeb814676b06669a3e4fe310717efe">XTG_PARAM_OP_ADDRMODE_CONST</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:aa9eeb814676b06669a3e4fe310717efe"><td class="mdescLeft">&#160;</td><td class="mdescRight">Constant Addr mode.  <a href="#aa9eeb814676b06669a3e4fe310717efe">More...</a><br /></td></tr>
<tr class="separator:aa9eeb814676b06669a3e4fe310717efe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a36f53cac2eca3c077bfc7691b4bae390"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a36f53cac2eca3c077bfc7691b4bae390">XTG_PARAM_OP_ADDRMODE_INCR</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:a36f53cac2eca3c077bfc7691b4bae390"><td class="mdescLeft">&#160;</td><td class="mdescRight">Increment Addr mode.  <a href="#a36f53cac2eca3c077bfc7691b4bae390">More...</a><br /></td></tr>
<tr class="separator:a36f53cac2eca3c077bfc7691b4bae390"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a277fae0e2fc80d4ee117d512dd487343"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a277fae0e2fc80d4ee117d512dd487343">XTG_PARAM_OP_ADDRMODE_RAND</a>&#160;&#160;&#160;2</td></tr>
<tr class="memdesc:a277fae0e2fc80d4ee117d512dd487343"><td class="mdescLeft">&#160;</td><td class="mdescRight">Random Addr mode.  <a href="#a277fae0e2fc80d4ee117d512dd487343">More...</a><br /></td></tr>
<tr class="separator:a277fae0e2fc80d4ee117d512dd487343"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a23774b21bbe0901e320b466de35008a2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a23774b21bbe0901e320b466de35008a2">XTG_PARAMOP_INTERVALMODE_CONST</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:a23774b21bbe0901e320b466de35008a2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Constant Interval mode.  <a href="#a23774b21bbe0901e320b466de35008a2">More...</a><br /></td></tr>
<tr class="separator:a23774b21bbe0901e320b466de35008a2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2b331214337314d34e905dd2d3b5c0a2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xtrafgen__hw_8h.html#a2b331214337314d34e905dd2d3b5c0a2">XTG_PARAMOP_INTERVALMODE_RAND</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:a2b331214337314d34e905dd2d3b5c0a2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Random Interval mode.  <a href="#a2b331214337314d34e905dd2d3b5c0a2">More...</a><br /></td></tr>
<tr class="separator:a2b331214337314d34e905dd2d3b5c0a2"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Macro Definition Documentation</h2>
<a id="a575795d7d5b2348195e02fd8cccabe39"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a575795d7d5b2348195e02fd8cccabe39">&#9670;&nbsp;</a></span>XTG_ADDR_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_ADDR_MASK&#160;&#160;&#160;0xFFFFFFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Driven to a*_addr line. </p>

</div>
</div>
<a id="a4fec29a2aedb84ed9410fe5298245d24"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a4fec29a2aedb84ed9410fe5298245d24">&#9670;&nbsp;</a></span>XTG_ADDR_SHIFT</h2>

<div class="memitem">
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      <table class="memname">
        <tr>
          <td class="memname">#define XTG_ADDR_SHIFT&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Driven to a*_addr line. </p>

</div>
</div>
<a id="ae149dfc387f997a33cbe70d57362fc0f"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ae149dfc387f997a33cbe70d57362fc0f">&#9670;&nbsp;</a></span>XTG_BURST_MASK</h2>

<div class="memitem">
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      <table class="memname">
        <tr>
          <td class="memname">#define XTG_BURST_MASK&#160;&#160;&#160;0x3</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Driven to a*_burst line. </p>

</div>
</div>
<a id="a70414e4d0c831df19899fe7c050a7a03"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a70414e4d0c831df19899fe7c050a7a03">&#9670;&nbsp;</a></span>XTG_BURST_SHIFT</h2>

<div class="memitem">
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      <table class="memname">
        <tr>
          <td class="memname">#define XTG_BURST_SHIFT&#160;&#160;&#160;10</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Driven to a*_burst line. </p>

</div>
</div>
<a id="a3b4631d92345fd27ee3e40d827a184f3"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a3b4631d92345fd27ee3e40d827a184f3">&#9670;&nbsp;</a></span>XTG_CACHE_MASK</h2>

<div class="memitem">
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      <table class="memname">
        <tr>
          <td class="memname">#define XTG_CACHE_MASK&#160;&#160;&#160;0xF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Driven to a*_cache line. </p>

</div>
</div>
<a id="a6496641578aa8a7a22dd3c6147221175"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a6496641578aa8a7a22dd3c6147221175">&#9670;&nbsp;</a></span>XTG_CACHE_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_CACHE_SHIFT&#160;&#160;&#160;4</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Driven to a*_cache line. </p>

</div>
</div>
<a id="a73aac9edd6e776525f4e44865ed7e481"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a73aac9edd6e776525f4e44865ed7e481">&#9670;&nbsp;</a></span>XTG_CFG_STS_MBASIC_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_CFG_STS_MBASIC_MASK&#160;&#160;&#160;0x00800000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Basic Mode. </p>

<p class="reference">Referenced by <a class="el" href="group__trafgen__v3__2.html#ga4d40f6d5551836dab49e0d22e8d5e1eb">XTrafGen_CfgInitialize()</a>.</p>

</div>
</div>
<a id="a1816012cab8ec1b93b06d20dde1e0128"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a1816012cab8ec1b93b06d20dde1e0128">&#9670;&nbsp;</a></span>XTG_CFG_STS_MFULL_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_CFG_STS_MFULL_MASK&#160;&#160;&#160;0x01000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Full Mode. </p>

<p class="reference">Referenced by <a class="el" href="group__trafgen__v3__2.html#ga4d40f6d5551836dab49e0d22e8d5e1eb">XTrafGen_CfgInitialize()</a>.</p>

</div>
</div>
<a id="a7387f793b21568825291b8ae05e9a8dc"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a7387f793b21568825291b8ae05e9a8dc">&#9670;&nbsp;</a></span>XTG_CFG_STS_MWIDTH_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_CFG_STS_MWIDTH_MASK&#160;&#160;&#160;0x70000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Master Width Mask. </p>

<p class="reference">Referenced by <a class="el" href="group__trafgen__v3__2.html#ga4d40f6d5551836dab49e0d22e8d5e1eb">XTrafGen_CfgInitialize()</a>.</p>

</div>
</div>
<a id="a43010263c928054845a6e4da818c5cb6"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a43010263c928054845a6e4da818c5cb6">&#9670;&nbsp;</a></span>XTG_CFG_STS_MWIDTH_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_CFG_STS_MWIDTH_SHIFT&#160;&#160;&#160;28</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Master Width Shift. </p>

<p class="reference">Referenced by <a class="el" href="group__trafgen__v3__2.html#ga4d40f6d5551836dab49e0d22e8d5e1eb">XTrafGen_CfgInitialize()</a>.</p>

</div>
</div>
<a id="a641638626484a52b81fbbf8f30bd45dc"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a641638626484a52b81fbbf8f30bd45dc">&#9670;&nbsp;</a></span>XTG_CFG_STS_SWIDTH_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_CFG_STS_SWIDTH_MASK&#160;&#160;&#160;0x0E000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Slave Width Mask. </p>

<p class="reference">Referenced by <a class="el" href="group__trafgen__v3__2.html#ga4d40f6d5551836dab49e0d22e8d5e1eb">XTrafGen_CfgInitialize()</a>.</p>

</div>
</div>
<a id="ab8521be4a5dc1628cb3a3afe87298843"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ab8521be4a5dc1628cb3a3afe87298843">&#9670;&nbsp;</a></span>XTG_CFG_STS_SWIDTH_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_CFG_STS_SWIDTH_SHIFT&#160;&#160;&#160;25</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Slave Width Shift. </p>

<p class="reference">Referenced by <a class="el" href="group__trafgen__v3__2.html#ga4d40f6d5551836dab49e0d22e8d5e1eb">XTrafGen_CfgInitialize()</a>.</p>

</div>
</div>
<a id="ad893dd4b8011e14e68b21afa20c019c8"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ad893dd4b8011e14e68b21afa20c019c8">&#9670;&nbsp;</a></span>XTG_EXPECTED_RESP_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_EXPECTED_RESP_MASK&#160;&#160;&#160;0x7</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Expected response. </p>

</div>
</div>
<a id="abc9721f5268f2b05074b669d5603b1e7"></a>
<h2 class="memtitle"><span class="permalink"><a href="#abc9721f5268f2b05074b669d5603b1e7">&#9670;&nbsp;</a></span>XTG_EXPECTED_RESP_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_EXPECTED_RESP_SHIFT&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Expected response. </p>

</div>
</div>
<a id="a5a7178fbdfb4b46aaa7bd0fc308ec636"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a5a7178fbdfb4b46aaa7bd0fc308ec636">&#9670;&nbsp;</a></span>XTG_ID_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_ID_MASK&#160;&#160;&#160;0x3F</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Driven to a*_id line. </p>

</div>
</div>
<a id="abf8893d48139c874e7628a7d32d1861b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#abf8893d48139c874e7628a7d32d1861b">&#9670;&nbsp;</a></span>XTG_ID_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_ID_SHIFT&#160;&#160;&#160;15</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Driven to a*_id line. </p>

</div>
</div>
<a id="a9267c6248c021a02be574f803f11c677"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a9267c6248c021a02be574f803f11c677">&#9670;&nbsp;</a></span>XTG_LAST_ADDR_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_LAST_ADDR_MASK&#160;&#160;&#160;0x7</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Last address. </p>

</div>
</div>
<a id="ab2e214bbd75cfa106a9cf34a075ca7c3"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ab2e214bbd75cfa106a9cf34a075ca7c3">&#9670;&nbsp;</a></span>XTG_LAST_ADDR_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_LAST_ADDR_SHIFT&#160;&#160;&#160;28</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Last address. </p>

</div>
</div>
<a id="a74fdcca6bba8dfbfd0ed288f9132bab0"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a74fdcca6bba8dfbfd0ed288f9132bab0">&#9670;&nbsp;</a></span>XTG_LEN_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_LEN_MASK&#160;&#160;&#160;0xFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Driven to a*_len line. </p>

</div>
</div>
<a id="ae25779b53195ced1e45d64bc53344c28"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ae25779b53195ced1e45d64bc53344c28">&#9670;&nbsp;</a></span>XTG_LEN_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_LEN_SHIFT&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Driven to a*_len line. </p>

</div>
</div>
<a id="a6575f2dffb01e56c6b38eda8190664b8"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a6575f2dffb01e56c6b38eda8190664b8">&#9670;&nbsp;</a></span>XTG_LOCK_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_LOCK_MASK&#160;&#160;&#160;0x1</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Driven to a*_lock line. </p>

</div>
</div>
<a id="a819696f324a87fbdf9dbce5c6aafcdaf"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a819696f324a87fbdf9dbce5c6aafcdaf">&#9670;&nbsp;</a></span>XTG_LOCK_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_LOCK_SHIFT&#160;&#160;&#160;8</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Driven to a*_lock line. </p>

</div>
</div>
<a id="a7f69f7e850cdf6eaeacb76be85d8ad51"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a7f69f7e850cdf6eaeacb76be85d8ad51">&#9670;&nbsp;</a></span>XTG_MSTERR_INTR_MINTREN_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_MSTERR_INTR_MINTREN_MASK&#160;&#160;&#160;0x00008000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Master Err Interrupt Enable. </p>

</div>
</div>
<a id="ae797ad9c3446d0523af686f5a1360a2e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ae797ad9c3446d0523af686f5a1360a2e">&#9670;&nbsp;</a></span>XTG_MSTRAM_INDEX_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_MSTRAM_INDEX_MASK&#160;&#160;&#160;0x1FFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Master RAM Index. </p>

</div>
</div>
<a id="adac26542aa0ea0c464a48d0c60086788"></a>
<h2 class="memtitle"><span class="permalink"><a href="#adac26542aa0ea0c464a48d0c60086788">&#9670;&nbsp;</a></span>XTG_MSTRAM_INDEX_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_MSTRAM_INDEX_SHIFT&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Master RAM Index. </p>

</div>
</div>
<a id="a23937f160c785883f46e3e8ac03af193"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a23937f160c785883f46e3e8ac03af193">&#9670;&nbsp;</a></span>XTG_MY_DEPEND_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_MY_DEPEND_MASK&#160;&#160;&#160;0x1FF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>My depend command no. </p>

</div>
</div>
<a id="a43673c92101ad1d1af680384add5f610"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a43673c92101ad1d1af680384add5f610">&#9670;&nbsp;</a></span>XTG_MY_DEPEND_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_MY_DEPEND_SHIFT&#160;&#160;&#160;22</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>My depend cmd num. </p>

</div>
</div>
<a id="a50464785b101e677032e4956a4592a0e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a50464785b101e677032e4956a4592a0e">&#9670;&nbsp;</a></span>XTG_OTHER_DEPEND_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_OTHER_DEPEND_MASK&#160;&#160;&#160;0x1FF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Other depend Command no. </p>

</div>
</div>
<a id="a18b2f14ba07703fe0e078d326496231d"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a18b2f14ba07703fe0e078d326496231d">&#9670;&nbsp;</a></span>XTG_OTHER_DEPEND_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_OTHER_DEPEND_SHIFT&#160;&#160;&#160;13</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Other depend cmd num. </p>

</div>
</div>
<a id="a1db016038b97b33a8f6ac84a1aeb9b05"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a1db016038b97b33a8f6ac84a1aeb9b05">&#9670;&nbsp;</a></span>XTG_PARAM_ADDRMODE_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_ADDRMODE_MASK&#160;&#160;&#160;0x3</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Address mode. </p>

</div>
</div>
<a id="a428fb28a58206c20a2bda291fd8966a4"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a428fb28a58206c20a2bda291fd8966a4">&#9670;&nbsp;</a></span>XTG_PARAM_ADDRMODE_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_ADDRMODE_SHIFT&#160;&#160;&#160;24</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Address mode. </p>

</div>
</div>
<a id="a04045088459eca529c1dc34dccdcc889"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a04045088459eca529c1dc34dccdcc889">&#9670;&nbsp;</a></span>XTG_PARAM_ADDRRANGE_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_ADDRRANGE_MASK&#160;&#160;&#160;0xF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Address Range. </p>

</div>
</div>
<a id="a0ecc1e7486d1e09d8e771674e163e215"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a0ecc1e7486d1e09d8e771674e163e215">&#9670;&nbsp;</a></span>XTG_PARAM_ADDRRANGE_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_ADDRRANGE_SHIFT&#160;&#160;&#160;20</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Address Range. </p>

</div>
</div>
<a id="ab433ce1c62131e78ac0d5376c85cfeab"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ab433ce1c62131e78ac0d5376c85cfeab">&#9670;&nbsp;</a></span>XTG_PARAM_COUNT_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_COUNT_MASK&#160;&#160;&#160;0xFFFFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Repeat/Delay count. </p>

</div>
</div>
<a id="aec8150e49af318bfd447d9b3cbf80734"></a>
<h2 class="memtitle"><span class="permalink"><a href="#aec8150e49af318bfd447d9b3cbf80734">&#9670;&nbsp;</a></span>XTG_PARAM_COUNT_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_COUNT_SHIFT&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Repeat/Delay count. </p>

</div>
</div>
<a id="ad8b0023a1d6151920452773820e2e1a0"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ad8b0023a1d6151920452773820e2e1a0">&#9670;&nbsp;</a></span>XTG_PARAM_DELAY_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_DELAY_MASK&#160;&#160;&#160;0xFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FIXED RPT Delay count. </p>

</div>
</div>
<a id="afd5037cc1466de72917fbcdd8c87e784"></a>
<h2 class="memtitle"><span class="permalink"><a href="#afd5037cc1466de72917fbcdd8c87e784">&#9670;&nbsp;</a></span>XTG_PARAM_DELAY_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_DELAY_SHIFT&#160;&#160;&#160;8</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FIXED RPT Delay count. </p>

</div>
</div>
<a id="ae2ffe39b97ed925d219f1abb0ce23916"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ae2ffe39b97ed925d219f1abb0ce23916">&#9670;&nbsp;</a></span>XTG_PARAM_DELAYRANGE_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_DELAYRANGE_MASK&#160;&#160;&#160;0xFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Delay Range. </p>

</div>
</div>
<a id="a67d17cf7158e597c2307e21521e35812"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a67d17cf7158e597c2307e21521e35812">&#9670;&nbsp;</a></span>XTG_PARAM_DELAYRANGE_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_DELAYRANGE_SHIFT&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Delay Range. </p>

</div>
</div>
<a id="a7358e0b257a66c3dea934297d4ce2e4c"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a7358e0b257a66c3dea934297d4ce2e4c">&#9670;&nbsp;</a></span>XTG_PARAM_IDMODE_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_IDMODE_MASK&#160;&#160;&#160;0x1</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Id mode. </p>

</div>
</div>
<a id="adf334f6bf0852006382b697cc4ab59ce"></a>
<h2 class="memtitle"><span class="permalink"><a href="#adf334f6bf0852006382b697cc4ab59ce">&#9670;&nbsp;</a></span>XTG_PARAM_IDMODE_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_IDMODE_SHIFT&#160;&#160;&#160;28</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Id mode. </p>

</div>
</div>
<a id="a5e5c93dc4a415adb31056d163fff03db"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a5e5c93dc4a415adb31056d163fff03db">&#9670;&nbsp;</a></span>XTG_PARAM_INTERVALMODE_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_INTERVALMODE_MASK&#160;&#160;&#160;0x3</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Interval mode. </p>

</div>
</div>
<a id="ac10bb6f9809e4f577bd36cb5dde0354e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ac10bb6f9809e4f577bd36cb5dde0354e">&#9670;&nbsp;</a></span>XTG_PARAM_INTERVALMODE_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_INTERVALMODE_SHIFT&#160;&#160;&#160;26</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Interval mode. </p>

</div>
</div>
<a id="aa9eeb814676b06669a3e4fe310717efe"></a>
<h2 class="memtitle"><span class="permalink"><a href="#aa9eeb814676b06669a3e4fe310717efe">&#9670;&nbsp;</a></span>XTG_PARAM_OP_ADDRMODE_CONST</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_OP_ADDRMODE_CONST&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Constant Addr mode. </p>

</div>
</div>
<a id="a36f53cac2eca3c077bfc7691b4bae390"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a36f53cac2eca3c077bfc7691b4bae390">&#9670;&nbsp;</a></span>XTG_PARAM_OP_ADDRMODE_INCR</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_OP_ADDRMODE_INCR&#160;&#160;&#160;1</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Increment Addr mode. </p>

</div>
</div>
<a id="a277fae0e2fc80d4ee117d512dd487343"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a277fae0e2fc80d4ee117d512dd487343">&#9670;&nbsp;</a></span>XTG_PARAM_OP_ADDRMODE_RAND</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_OP_ADDRMODE_RAND&#160;&#160;&#160;2</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Random Addr mode. </p>

</div>
</div>
<a id="a888fa5e45c08153523c902eacb4078a8"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a888fa5e45c08153523c902eacb4078a8">&#9670;&nbsp;</a></span>XTG_PARAM_OP_DELAY</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_OP_DELAY&#160;&#160;&#160;2</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Delay mode. </p>

</div>
</div>
<a id="a64bfe0cfa6be21facf834f5d49c2a706"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a64bfe0cfa6be21facf834f5d49c2a706">&#9670;&nbsp;</a></span>XTG_PARAM_OP_FIXEDRPT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_OP_FIXEDRPT&#160;&#160;&#160;3</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Fixed Repeat Delay. </p>

</div>
</div>
<a id="a65d8f9067f4a40826da17eca055cac9e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a65d8f9067f4a40826da17eca055cac9e">&#9670;&nbsp;</a></span>XTG_PARAM_OP_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_OP_MASK&#160;&#160;&#160;0x7</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Opcode. </p>

</div>
</div>
<a id="a71baeb60d7cd7baa527e7d87378632c0"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a71baeb60d7cd7baa527e7d87378632c0">&#9670;&nbsp;</a></span>XTG_PARAM_OP_NOP</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_OP_NOP&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>NOP mode. </p>

</div>
</div>
<a id="ad4415c801c23c948e6c180ad252e0d8f"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ad4415c801c23c948e6c180ad252e0d8f">&#9670;&nbsp;</a></span>XTG_PARAM_OP_RPT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_OP_RPT&#160;&#160;&#160;1</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Repeat mode. </p>

</div>
</div>
<a id="a120a164368673bb038500e599e1501ea"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a120a164368673bb038500e599e1501ea">&#9670;&nbsp;</a></span>XTG_PARAM_OP_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAM_OP_SHIFT&#160;&#160;&#160;29</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Opcode. </p>

</div>
</div>
<a id="a23774b21bbe0901e320b466de35008a2"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a23774b21bbe0901e320b466de35008a2">&#9670;&nbsp;</a></span>XTG_PARAMOP_INTERVALMODE_CONST</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAMOP_INTERVALMODE_CONST&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Constant Interval mode. </p>

</div>
</div>
<a id="a2b331214337314d34e905dd2d3b5c0a2"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a2b331214337314d34e905dd2d3b5c0a2">&#9670;&nbsp;</a></span>XTG_PARAMOP_INTERVALMODE_RAND</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PARAMOP_INTERVALMODE_RAND&#160;&#160;&#160;1</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Random Interval mode. </p>

</div>
</div>
<a id="ae6b714a335a4b02967a37f0ead14508a"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ae6b714a335a4b02967a37f0ead14508a">&#9670;&nbsp;</a></span>XTG_PROT_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PROT_MASK&#160;&#160;&#160;0x7</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Driven to a*_prot line. </p>

</div>
</div>
<a id="a0796a27df8444fd763ccd6c0356aa8e4"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a0796a27df8444fd763ccd6c0356aa8e4">&#9670;&nbsp;</a></span>XTG_PROT_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_PROT_SHIFT&#160;&#160;&#160;21</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Driven to a*_prot line. </p>

</div>
</div>
<a id="a31f414339e85047271ed193829b066b6"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a31f414339e85047271ed193829b066b6">&#9670;&nbsp;</a></span>XTG_QOS_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_QOS_MASK&#160;&#160;&#160;0xF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Driven to a*_qos line. </p>

</div>
</div>
<a id="ae3f2ee00c71bc8f847738acf83bf1c5c"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ae3f2ee00c71bc8f847738acf83bf1c5c">&#9670;&nbsp;</a></span>XTG_QOS_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_QOS_SHIFT&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Driven to a*_qos line. </p>

</div>
</div>
<a id="acba37550ee94c7c7022aa5a3ad946fc3"></a>
<h2 class="memtitle"><span class="permalink"><a href="#acba37550ee94c7c7022aa5a3ad946fc3">&#9670;&nbsp;</a></span>XTG_SIZE_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_SIZE_MASK&#160;&#160;&#160;0x7</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Driven to a*_size line. </p>

</div>
</div>
<a id="a6523ef7f08423cbc5150e3d6e55abd99"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a6523ef7f08423cbc5150e3d6e55abd99">&#9670;&nbsp;</a></span>XTG_SIZE_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_SIZE_SHIFT&#160;&#160;&#160;12</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Driven to a*_size line. </p>

</div>
</div>
<a id="a4955ccf9832cc09dd5f05b54f49104dd"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a4955ccf9832cc09dd5f05b54f49104dd">&#9670;&nbsp;</a></span>XTG_STATIC_CNTL_RESET_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STATIC_CNTL_RESET_MASK&#160;&#160;&#160;0x00000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Static Disable Mask. </p>

</div>
</div>
<a id="a820c08467cb0fc69af91e8747bf52199"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a820c08467cb0fc69af91e8747bf52199">&#9670;&nbsp;</a></span>XTG_STATIC_CNTL_STEN_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STATIC_CNTL_STEN_MASK&#160;&#160;&#160;0x00000001</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Static enable Mask. </p>

</div>
</div>
<a id="ae82296e2d81edb5da14c813e36b604cc"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ae82296e2d81edb5da14c813e36b604cc">&#9670;&nbsp;</a></span>XTG_STATIC_CNTL_TD_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STATIC_CNTL_TD_MASK&#160;&#160;&#160;0x00000002</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Transfer Done Mask. </p>

</div>
</div>
<a id="ac0e75db08cd3774207a38bdfe78f2ac9"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ac0e75db08cd3774207a38bdfe78f2ac9">&#9670;&nbsp;</a></span>XTG_STATIC_CNTL_TD_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STATIC_CNTL_TD_SHIFT&#160;&#160;&#160;1</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Transfer Done Shift. </p>

</div>
</div>
<a id="a2f470f08ec693fff5af6c5109f1b3ffc"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a2f470f08ec693fff5af6c5109f1b3ffc">&#9670;&nbsp;</a></span>XTG_STATIC_CNTL_VER_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STATIC_CNTL_VER_MASK&#160;&#160;&#160;0xFF000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Version Mask. </p>

</div>
</div>
<a id="a128106d0d3435137e96192b0386eeec4"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a128106d0d3435137e96192b0386eeec4">&#9670;&nbsp;</a></span>XTG_STATIC_CNTL_VER_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STATIC_CNTL_VER_SHIFT&#160;&#160;&#160;24</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Version Shift. </p>

</div>
</div>
<a id="a6a65cb71fdd0717246547dbbe16b6e1b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a6a65cb71fdd0717246547dbbe16b6e1b">&#9670;&nbsp;</a></span>XTG_STATIC_LEN_BLEN_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STATIC_LEN_BLEN_MASK&#160;&#160;&#160;0x000000FF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Burst length Mask. </p>

</div>
</div>
<a id="a490ccc5cf897e6daf0e403fdb5028cc8"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a490ccc5cf897e6daf0e403fdb5028cc8">&#9670;&nbsp;</a></span>XTG_STREAM_CFG_PDLY_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STREAM_CFG_PDLY_MASK&#160;&#160;&#160;0xFFFF0000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Programmable Delay Mask. </p>

</div>
</div>
<a id="aea7d215adbbf69b18fac485e2d150bd9"></a>
<h2 class="memtitle"><span class="permalink"><a href="#aea7d215adbbf69b18fac485e2d150bd9">&#9670;&nbsp;</a></span>XTG_STREAM_CFG_PDLY_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STREAM_CFG_PDLY_SHIFT&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Programmable Delay Shift. </p>

</div>
</div>
<a id="ae44681fc73afbcdb7ae0015719f8ac47"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ae44681fc73afbcdb7ae0015719f8ac47">&#9670;&nbsp;</a></span>XTG_STREAM_CFG_RANDL_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STREAM_CFG_RANDL_MASK&#160;&#160;&#160;0x00000001</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Random Length Mask. </p>

</div>
</div>
<a id="ae6da854602744d63b3fe0dfdc2dc22f9"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ae6da854602744d63b3fe0dfdc2dc22f9">&#9670;&nbsp;</a></span>XTG_STREAM_CFG_RANDLY_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STREAM_CFG_RANDLY_MASK&#160;&#160;&#160;0x00000002</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Random Delay Mask. </p>

</div>
</div>
<a id="ae0436a212983ec018bba1d0a4352f32f"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ae0436a212983ec018bba1d0a4352f32f">&#9670;&nbsp;</a></span>XTG_STREAM_CFG_RANDLY_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STREAM_CFG_RANDLY_SHIFT&#160;&#160;&#160;1</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Random Delay Shift. </p>

</div>
</div>
<a id="a27be0cf2c90513010b73b0b8db1163dc"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a27be0cf2c90513010b73b0b8db1163dc">&#9670;&nbsp;</a></span>XTG_STREAM_CFG_TDEST_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STREAM_CFG_TDEST_MASK&#160;&#160;&#160;0x0000FF00</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TDEST PORT Mask. </p>

</div>
</div>
<a id="acf47f8d5a9f92da3d0d5b4fd6be627a6"></a>
<h2 class="memtitle"><span class="permalink"><a href="#acf47f8d5a9f92da3d0d5b4fd6be627a6">&#9670;&nbsp;</a></span>XTG_STREAM_CFG_TDEST_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STREAM_CFG_TDEST_SHIFT&#160;&#160;&#160;8</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TDEST PORT Shift. </p>

</div>
</div>
<a id="ad4ac7a7ef3c84748869c001e04d5dade"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ad4ac7a7ef3c84748869c001e04d5dade">&#9670;&nbsp;</a></span>XTG_STREAM_CNTL_RESET_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STREAM_CNTL_RESET_MASK&#160;&#160;&#160;0x00000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Streaming Disable Mask. </p>

</div>
</div>
<a id="a96e6916449a1ded46ea7882b67d2d732"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a96e6916449a1ded46ea7882b67d2d732">&#9670;&nbsp;</a></span>XTG_STREAM_CNTL_STEN_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STREAM_CNTL_STEN_MASK&#160;&#160;&#160;0x00000001</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Streaming Enable Mask. </p>

</div>
</div>
<a id="a4b0674a7c9f7879bf6462860641b4d89"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a4b0674a7c9f7879bf6462860641b4d89">&#9670;&nbsp;</a></span>XTG_STREAM_CNTL_TD_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STREAM_CNTL_TD_MASK&#160;&#160;&#160;0x00000002</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Transfer Done Mask. </p>

</div>
</div>
<a id="a3e492e71798bc4139c136551452503fa"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a3e492e71798bc4139c136551452503fa">&#9670;&nbsp;</a></span>XTG_STREAM_CNTL_TD_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STREAM_CNTL_TD_SHIFT&#160;&#160;&#160;1</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Transfer Done Shift. </p>

</div>
</div>
<a id="a33aba05b605e1929b2045d76228f04f5"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a33aba05b605e1929b2045d76228f04f5">&#9670;&nbsp;</a></span>XTG_STREAM_CNTL_VER_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STREAM_CNTL_VER_MASK&#160;&#160;&#160;0xFF000000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Version Mask. </p>

</div>
</div>
<a id="a49c88fdab76f14bbf070eebcedc16ef1"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a49c88fdab76f14bbf070eebcedc16ef1">&#9670;&nbsp;</a></span>XTG_STREAM_CNTL_VER_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STREAM_CNTL_VER_SHIFT&#160;&#160;&#160;24</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Version Shift. </p>

</div>
</div>
<a id="a556bcb7b08d4170167ee65c08c7a0ebe"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a556bcb7b08d4170167ee65c08c7a0ebe">&#9670;&nbsp;</a></span>XTG_STREAM_TL_TCNT_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STREAM_TL_TCNT_MASK&#160;&#160;&#160;0xFFFF0000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Transfer Count Mask. </p>

</div>
</div>
<a id="a826017ee56ef1171a4d132dc12ca8341"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a826017ee56ef1171a4d132dc12ca8341">&#9670;&nbsp;</a></span>XTG_STREAM_TL_TCNT_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STREAM_TL_TCNT_SHIFT&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Transfer Count Shift. </p>

</div>
</div>
<a id="ae28f53acd7ef1f38265f560c17c64800"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ae28f53acd7ef1f38265f560c17c64800">&#9670;&nbsp;</a></span>XTG_STREAM_TL_TLEN_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_STREAM_TL_TLEN_MASK&#160;&#160;&#160;0x0000FFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Transfer Length Mask. </p>

</div>
</div>
<a id="a6dda4f385ddd7962f4b7978fc1c42664"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a6dda4f385ddd7962f4b7978fc1c42664">&#9670;&nbsp;</a></span>XTG_USER_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_USER_MASK&#160;&#160;&#160;0xFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Driven to a*_user line. </p>

</div>
</div>
<a id="a280ef09f695b10f97848ce74d68f7c02"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a280ef09f695b10f97848ce74d68f7c02">&#9670;&nbsp;</a></span>XTG_USER_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_USER_SHIFT&#160;&#160;&#160;8</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Driven to a*_user line. </p>

</div>
</div>
<a id="a584b02e4845e493b2854d3c865aaed19"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a584b02e4845e493b2854d3c865aaed19">&#9670;&nbsp;</a></span>XTG_VALID_CMD_MASK</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_VALID_CMD_MASK&#160;&#160;&#160;0x1</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Valid Command. </p>

</div>
</div>
<a id="a4387f942768e60fd471499c63ad5e7dd"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a4387f942768e60fd471499c63ad5e7dd">&#9670;&nbsp;</a></span>XTG_VALID_CMD_SHIFT</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTG_VALID_CMD_SHIFT&#160;&#160;&#160;31</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Valid Command. </p>

</div>
</div>
<a id="a04a570c3b4cc407d745237050374013c"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a04a570c3b4cc407d745237050374013c">&#9670;&nbsp;</a></span>XTrafGen_ReadCmdRam</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTrafGen_ReadCmdRam</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Offset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;(Xil_In32(((BaseAddress) + <a class="el" href="group__trafgen__v3__2.html#ga1b4f5daeb95b5827db0760c1c0dc13e5">XTG_COMMAND_RAM_OFFSET</a> + (Offset))))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>XTrafGen_ReadCmdRam returns the value read from the Command RAM specified by <em>Offset</em>. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the Axi TrafGen device. </td></tr>
    <tr><td class="paramname">Offset</td><td>is the offset of the Command RAM to be read.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Returns the 32-bit value of the memory location.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="xtrafgen__hw_8h.html#a04a570c3b4cc407d745237050374013c" title="XTrafGen_ReadCmdRam returns the value read from the Command RAM specified by Offset. ">XTrafGen_ReadCmdRam(u32 BaseAddress, u32 Offset)</a> </dd></dl>

</div>
</div>
<a id="ab9c29e9e8361e7dc553c689e7cfd8ee1"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ab9c29e9e8361e7dc553c689e7cfd8ee1">&#9670;&nbsp;</a></span>XTrafGen_ReadCmdRam_Msb</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTrafGen_ReadCmdRam_Msb</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Offset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;(Xil_In32(((BaseAddress) + <a class="el" href="group__trafgen__v3__2.html#ga6fd650735d7eb15cc3cd76679f8b7894">XTG_COMMAND_RAM_MSB_OFFSET</a> + (Offset))))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>XTrafGen_ReadCmdRam_Msb returns the value read from the Command RAM specified by <em>Offset</em>. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the MSB of base address of the Axi TrafGen device. </td></tr>
    <tr><td class="paramname">Offset</td><td>is the offset of the Command RAM to be read.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Returns the 32-bit value of the memory location.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="xtrafgen__hw_8h.html#ab9c29e9e8361e7dc553c689e7cfd8ee1" title="XTrafGen_ReadCmdRam_Msb returns the value read from the Command RAM specified by Offset. ">XTrafGen_ReadCmdRam_Msb(u32 BaseAddress, u32 Offset)</a> </dd></dl>

</div>
</div>
<a id="a60ceec5d839e8a8f1cdda74c93c425b8"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a60ceec5d839e8a8f1cdda74c93c425b8">&#9670;&nbsp;</a></span>XTrafGen_ReadMasterRam</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTrafGen_ReadMasterRam</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Offset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;(Xil_In32(((BaseAddress) + <a class="el" href="group__trafgen__v3__2.html#ga5f8872e23f0ea33fda1193c114fa9224">XTG_MASTER_RAM_OFFSET</a> + (Offset))))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>XTrafGen_ReadMasterRam returns the value read from the Master RAM specified by <em>Offset</em>. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the Axi TrafGen device. </td></tr>
    <tr><td class="paramname">Offset</td><td>is the offset of the Master RAM to be read.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Returns the 32-bit value of the memory location.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="xtrafgen__hw_8h.html#a60ceec5d839e8a8f1cdda74c93c425b8" title="XTrafGen_ReadMasterRam returns the value read from the Master RAM specified by Offset. ">XTrafGen_ReadMasterRam(u32 BaseAddress, u32 Offset)</a> </dd></dl>

<p class="reference">Referenced by <a class="el" href="group__trafgen__v3__2.html#gaaea625b89454268bbbe7f93e309141c4">XTrafGen_AccessMasterRam()</a>.</p>

</div>
</div>
<a id="a29995f5e78072a8756081fed9ccb36bd"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a29995f5e78072a8756081fed9ccb36bd">&#9670;&nbsp;</a></span>XTrafGen_ReadParamRam</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTrafGen_ReadParamRam</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Offset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;(Xil_In32(((BaseAddress) + <a class="el" href="group__trafgen__v3__2.html#ga3252ba966b4231b39738858474879b33">XTG_PARAM_RAM_OFFSET</a> + (Offset))))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>XTrafGen_ReadParamRam returns the value read from the Parameter RAM specified by <em>Offset</em>. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the Axi TrafGen device. </td></tr>
    <tr><td class="paramname">Offset</td><td>is the offset of the Parameter RAM to be read.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Returns the 32-bit value of the memory location.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="xtrafgen__hw_8h.html#a29995f5e78072a8756081fed9ccb36bd" title="XTrafGen_ReadParamRam returns the value read from the Parameter RAM specified by Offset. ">XTrafGen_ReadParamRam(u32 BaseAddress, u32 Offset)</a> </dd></dl>

</div>
</div>
<a id="affb7c95abd8cad50d7efa83f94ea3344"></a>
<h2 class="memtitle"><span class="permalink"><a href="#affb7c95abd8cad50d7efa83f94ea3344">&#9670;&nbsp;</a></span>XTrafGen_ReadReg</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTrafGen_ReadReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;(Xil_In32(((BaseAddress) + (RegOffset))))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>XTrafGen_ReadReg returns the value read from the register specified by <em>RegOffset</em>. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the Axi TrafGen device. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the offset of the register to be read.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Returns the 32-bit value of the register.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="xtrafgen__hw_8h.html#affb7c95abd8cad50d7efa83f94ea3344" title="XTrafGen_ReadReg returns the value read from the register specified by RegOffset. ...">XTrafGen_ReadReg(u32 BaseAddress, u32 RegOffset)</a> </dd></dl>

</div>
</div>
<a id="a25bf6ea33be9bb74e718dc810c6760f5"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a25bf6ea33be9bb74e718dc810c6760f5">&#9670;&nbsp;</a></span>XTrafGen_WriteCmdRam</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTrafGen_WriteCmdRam</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Offset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Data&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;Xil_Out32(((BaseAddress) + <a class="el" href="group__trafgen__v3__2.html#ga1b4f5daeb95b5827db0760c1c0dc13e5">XTG_COMMAND_RAM_OFFSET</a> + (Offset)), (Data))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>XTrafGen_WriteCmdRam, writes <em>Data</em> to the Command RAM specified by <em>Offset</em>. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the Axi TrafGen device. </td></tr>
    <tr><td class="paramname">Offset</td><td>is the offset of the location in Command RAM to be written. </td></tr>
    <tr><td class="paramname">Data</td><td>is the 32-bit value to write to the Command RAM.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xtrafgen__hw_8h.html#a25bf6ea33be9bb74e718dc810c6760f5" title="XTrafGen_WriteCmdRam, writes Data to the Command RAM specified by Offset. ">XTrafGen_WriteCmdRam(u32 BaseAddress, u32 Offset, u32 Data)</a> </dd></dl>

</div>
</div>
<a id="afebb93dc8864de6d9466a5fd6355c117"></a>
<h2 class="memtitle"><span class="permalink"><a href="#afebb93dc8864de6d9466a5fd6355c117">&#9670;&nbsp;</a></span>XTrafGen_WriteCmdRam_Msb</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTrafGen_WriteCmdRam_Msb</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Offset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Data&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;Xil_Out32(((BaseAddress) + <a class="el" href="group__trafgen__v3__2.html#ga6fd650735d7eb15cc3cd76679f8b7894">XTG_COMMAND_RAM_MSB_OFFSET</a> + (Offset)), (Data))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>XTrafGen_WriteCmdRam_Msb, writes <em>Data</em> to the Command RAM specified by <em>Offset</em>. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the MSB of base address of the Axi TrafGen device. </td></tr>
    <tr><td class="paramname">Offset</td><td>is the offset of the location in Command RAM to be written. </td></tr>
    <tr><td class="paramname">Data</td><td>is the 32-bit value to write to the Command RAM.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xtrafgen__hw_8h.html#afebb93dc8864de6d9466a5fd6355c117" title="XTrafGen_WriteCmdRam_Msb, writes Data to the Command RAM specified by Offset. ">XTrafGen_WriteCmdRam_Msb(u32 BaseAddress, u32 Offset, u32 Data)</a> </dd></dl>

</div>
</div>
<a id="a8fe8b5ce12fefb6bba6acee1b89cb2a7"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a8fe8b5ce12fefb6bba6acee1b89cb2a7">&#9670;&nbsp;</a></span>XTrafGen_WriteMasterRam</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTrafGen_WriteMasterRam</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Offset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Data&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;Xil_Out32(((BaseAddress) + <a class="el" href="group__trafgen__v3__2.html#ga5f8872e23f0ea33fda1193c114fa9224">XTG_MASTER_RAM_OFFSET</a> + (Offset)), (Data))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>XTrafGen_WriteMasterRam, writes <em>Data</em> to the Master RAM specified by <em>Offset</em>. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the Axi TrafGen device. </td></tr>
    <tr><td class="paramname">Offset</td><td>is the offset of the location in Master RAM to be written. </td></tr>
    <tr><td class="paramname">Data</td><td>is the 32-bit value to write to the Master RAM.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xtrafgen__hw_8h.html#a8fe8b5ce12fefb6bba6acee1b89cb2a7" title="XTrafGen_WriteMasterRam, writes Data to the Master RAM specified by Offset. ">XTrafGen_WriteMasterRam(u32 BaseAddress, u32 Offset, u32 Data)</a> </dd></dl>

<p class="reference">Referenced by <a class="el" href="group__trafgen__v3__2.html#gaaea625b89454268bbbe7f93e309141c4">XTrafGen_AccessMasterRam()</a>.</p>

</div>
</div>
<a id="affbc767805f25351f801dc04114d513f"></a>
<h2 class="memtitle"><span class="permalink"><a href="#affbc767805f25351f801dc04114d513f">&#9670;&nbsp;</a></span>XTrafGen_WriteParamRam</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTrafGen_WriteParamRam</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Offset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Data&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;Xil_Out32(((BaseAddress) + <a class="el" href="group__trafgen__v3__2.html#ga3252ba966b4231b39738858474879b33">XTG_PARAM_RAM_OFFSET</a> + (Offset)), (Data))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>XTrafGen_WriteParamRam, writes <em>Data</em> to the Parameter RAM specified by <em>Offset</em>. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the Axi TrafGen device. </td></tr>
    <tr><td class="paramname">Offset</td><td>is the offset of the location in Parameter RAM to be written. </td></tr>
    <tr><td class="paramname">Data</td><td>is the 32-bit value to write to the Parameter RAM.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xtrafgen__hw_8h.html#affbc767805f25351f801dc04114d513f" title="XTrafGen_WriteParamRam, writes Data to the Parameter RAM specified by Offset. ">XTrafGen_WriteParamRam(u32 BaseAddress, u32 Offset, u32 Data)</a> </dd></dl>

</div>
</div>
<a id="ac6e57b26c1f5674deb7c571dc319bf9e"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ac6e57b26c1f5674deb7c571dc319bf9e">&#9670;&nbsp;</a></span>XTrafGen_WriteReg</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XTrafGen_WriteReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Data&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;Xil_Out32(((BaseAddress) + (RegOffset)), (Data))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>XTrafGen_WriteReg, writes <em>Data</em> to the register specified by <em>RegOffset</em>. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the Axi TrafGen device. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the offset of the register to be written. </td></tr>
    <tr><td class="paramname">Data</td><td>is the 32-bit value to write to the register.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xtrafgen__hw_8h.html#ac6e57b26c1f5674deb7c571dc319bf9e" title="XTrafGen_WriteReg, writes Data to the register specified by RegOffset. ">XTrafGen_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)</a> </dd></dl>

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